From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Cc: "Peter Crosthwaite" <peter.crosthwaite@xilinx.com>,
patches@linaro.org,
"Edgar E. Iglesias" <edgar.iglesias@gmail.com>,
"Greg Bellows" <greg.bellows@linaro.org>,
"Paolo Bonzini" <pbonzini@redhat.com>,
"Alex Bennée" <alex.bennee@linaro.org>,
"Richard Henderson" <rth@twiddle.net>
Subject: [Qemu-devel] [PATCH 09/14] exec.c: Capture the memory attributes for a watchpoint hit
Date: Tue, 7 Apr 2015 21:09:55 +0100 [thread overview]
Message-ID: <1428437400-8474-10-git-send-email-peter.maydell@linaro.org> (raw)
In-Reply-To: <1428437400-8474-1-git-send-email-peter.maydell@linaro.org>
Capture the memory attributes for the transaction which triggered
a watchpoint; this allows CPU specific code to implement features
like ARM's "user-mode only WPs also hit for LDRT/STRT accesses
made from privileged code".
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
exec.c | 52 +++++++++++++++++++++++++++++++---------------------
include/qom/cpu.h | 2 ++
2 files changed, 33 insertions(+), 21 deletions(-)
diff --git a/exec.c b/exec.c
index a0d18ee..b6a11c0 100644
--- a/exec.c
+++ b/exec.c
@@ -1858,7 +1858,7 @@ static const MemoryRegionOps notdirty_mem_ops = {
};
/* Generate a debug exception if a watchpoint has been hit. */
-static void check_watchpoint(int offset, int len, int flags)
+static void check_watchpoint(int offset, int len, MemTxAttrs attrs, int flags)
{
CPUState *cpu = current_cpu;
CPUArchState *env = cpu->env_ptr;
@@ -1884,6 +1884,7 @@ static void check_watchpoint(int offset, int len, int flags)
wp->flags |= BP_WATCHPOINT_HIT_WRITE;
}
wp->hitaddr = vaddr;
+ wp->hitattrs = attrs;
if (!cpu->watchpoint_hit) {
cpu->watchpoint_hit = wp;
tb_check_watchpoint(cpu);
@@ -1905,45 +1906,54 @@ static void check_watchpoint(int offset, int len, int flags)
/* Watchpoint access routines. Watchpoints are inserted using TLB tricks,
so these check for a hit then pass through to the normal out-of-line
phys routines. */
-static uint64_t watch_mem_read(void *opaque, hwaddr addr,
- unsigned size)
+static MemTxResult watch_mem_read(void *opaque, hwaddr addr, uint64_t *pdata,
+ unsigned size, MemTxAttrs attrs)
{
- check_watchpoint(addr & ~TARGET_PAGE_MASK, size, BP_MEM_READ);
+ MemTxResult res;
+ uint64_t data;
+
+ check_watchpoint(addr & ~TARGET_PAGE_MASK, size, attrs, BP_MEM_READ);
switch (size) {
- case 1: return address_space_ldub(&address_space_memory, addr,
- MEMTXATTRS_UNSPECIFIED, NULL);
- case 2: return address_space_lduw(&address_space_memory, addr,
- MEMTXATTRS_UNSPECIFIED, NULL);
- case 4: return address_space_ldl(&address_space_memory, addr,
- MEMTXATTRS_UNSPECIFIED, NULL);
+ case 1:
+ data = address_space_ldub(&address_space_memory, addr, attrs, &res);
+ break;
+ case 2:
+ data = address_space_lduw(&address_space_memory, addr, attrs, &res);
+ break;
+ case 4:
+ data = address_space_ldl(&address_space_memory, addr, attrs, &res);
+ break;
default: abort();
}
+ *pdata = data;
+ return res;
}
-static void watch_mem_write(void *opaque, hwaddr addr,
- uint64_t val, unsigned size)
+static MemTxResult watch_mem_write(void *opaque, hwaddr addr,
+ uint64_t val, unsigned size,
+ MemTxAttrs attrs)
{
- check_watchpoint(addr & ~TARGET_PAGE_MASK, size, BP_MEM_WRITE);
+ MemTxResult res;
+
+ check_watchpoint(addr & ~TARGET_PAGE_MASK, size, attrs, BP_MEM_WRITE);
switch (size) {
case 1:
- address_space_stb(&address_space_memory, addr, val,
- MEMTXATTRS_UNSPECIFIED, NULL);
+ address_space_stb(&address_space_memory, addr, val, attrs, &res);
break;
case 2:
- address_space_stw(&address_space_memory, addr, val,
- MEMTXATTRS_UNSPECIFIED, NULL);
+ address_space_stw(&address_space_memory, addr, val, attrs, &res);
break;
case 4:
- address_space_stl(&address_space_memory, addr, val,
- MEMTXATTRS_UNSPECIFIED, NULL);
+ address_space_stl(&address_space_memory, addr, val, attrs, &res);
break;
default: abort();
}
+ return res;
}
static const MemoryRegionOps watch_mem_ops = {
- .read = watch_mem_read,
- .write = watch_mem_write,
+ .read_with_attrs = watch_mem_read,
+ .write_with_attrs = watch_mem_write,
.endianness = DEVICE_NATIVE_ENDIAN,
};
diff --git a/include/qom/cpu.h b/include/qom/cpu.h
index 9dafb48..39f0f19 100644
--- a/include/qom/cpu.h
+++ b/include/qom/cpu.h
@@ -24,6 +24,7 @@
#include <setjmp.h>
#include "hw/qdev-core.h"
#include "exec/hwaddr.h"
+#include "exec/memattrs.h"
#include "qemu/queue.h"
#include "qemu/thread.h"
#include "qemu/tls.h"
@@ -195,6 +196,7 @@ typedef struct CPUWatchpoint {
vaddr vaddr;
vaddr len;
vaddr hitaddr;
+ MemTxAttrs hitattrs;
int flags; /* BP_* */
QTAILQ_ENTRY(CPUWatchpoint) entry;
} CPUWatchpoint;
--
1.9.1
next prev parent reply other threads:[~2015-04-07 20:10 UTC|newest]
Thread overview: 56+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-04-07 20:09 [Qemu-devel] [PATCH 00/14] Add memory attributes and use them in ARM Peter Maydell
2015-04-07 20:09 ` [Qemu-devel] [PATCH 01/14] memory: Define API for MemoryRegionOps to take attrs and return status Peter Maydell
2015-04-08 10:49 ` Paolo Bonzini
2015-04-09 8:55 ` Edgar E. Iglesias
2015-04-09 9:04 ` Peter Maydell
2015-04-09 9:21 ` Paolo Bonzini
2015-04-10 2:07 ` Edgar E. Iglesias
2015-04-10 14:51 ` Peter Maydell
2015-04-11 10:27 ` Edgar E. Iglesias
2015-04-09 9:32 ` Edgar E. Iglesias
2015-04-07 20:09 ` [Qemu-devel] [PATCH 02/14] memory: Add MemTxAttrs, MemTxResult to io_mem_read and io_mem_write Peter Maydell
2015-04-08 10:51 ` Paolo Bonzini
2015-04-08 10:59 ` Peter Maydell
2015-04-08 11:13 ` Paolo Bonzini
2015-04-09 8:59 ` Edgar E. Iglesias
2015-04-07 20:09 ` [Qemu-devel] [PATCH 03/14] Make CPU iotlb a structure rather than a plain hwaddr Peter Maydell
2015-04-08 10:52 ` Paolo Bonzini
2015-04-09 9:02 ` Edgar E. Iglesias
2015-04-07 20:09 ` [Qemu-devel] [PATCH 04/14] Add MemTxAttrs to the IOTLB Peter Maydell
2015-04-08 10:53 ` Paolo Bonzini
2015-04-09 9:04 ` Edgar E. Iglesias
2015-04-07 20:09 ` [Qemu-devel] [PATCH 05/14] exec.c: Convert subpage memory ops to _with_attrs Peter Maydell
2015-04-08 10:54 ` Paolo Bonzini
2015-04-09 9:07 ` Edgar E. Iglesias
2015-04-07 20:09 ` [Qemu-devel] [PATCH 06/14] exec.c: Make address_space_rw take transaction attributes Peter Maydell
2015-04-08 12:55 ` Paolo Bonzini
2015-04-09 9:59 ` Edgar E. Iglesias
2015-04-09 10:14 ` Peter Maydell
2015-04-09 10:21 ` Paolo Bonzini
2015-04-09 10:43 ` Peter Maydell
2015-04-09 11:40 ` Paolo Bonzini
2015-04-09 11:43 ` Peter Maydell
2015-04-07 20:09 ` [Qemu-devel] [PATCH 07/14] exec.c: Add new address_space_ld*/st* functions Peter Maydell
2015-04-08 11:03 ` Paolo Bonzini
2015-04-09 11:49 ` Peter Maydell
2015-04-09 12:00 ` Paolo Bonzini
2015-04-09 12:38 ` Peter Maydell
2015-04-09 12:42 ` Paolo Bonzini
2015-04-09 10:34 ` Edgar E. Iglesias
2015-04-07 20:09 ` [Qemu-devel] [PATCH 08/14] Switch non-CPU callers from ld/st*_phys to address_space_ld/st* Peter Maydell
2015-04-09 10:44 ` Edgar E. Iglesias
2015-04-07 20:09 ` Peter Maydell [this message]
2015-04-08 11:04 ` [Qemu-devel] [PATCH 09/14] exec.c: Capture the memory attributes for a watchpoint hit Paolo Bonzini
2015-04-08 11:14 ` Peter Maydell
2015-04-07 20:09 ` [Qemu-devel] [PATCH 10/14] target-arm: Honour NS bits in page tables Peter Maydell
2015-04-09 11:23 ` Edgar E. Iglesias
2015-04-09 14:14 ` Peter Maydell
2015-04-09 14:23 ` Edgar E. Iglesias
2015-04-07 20:09 ` [Qemu-devel] [PATCH 11/14] target-arm: Use correct memory attributes for page table walks Peter Maydell
2015-04-09 11:34 ` Edgar E. Iglesias
2015-04-07 20:09 ` [Qemu-devel] [PATCH 12/14] target-arm: Add user-mode transaction attribute Peter Maydell
2015-04-07 20:09 ` [Qemu-devel] [PATCH 13/14] target-arm: Use attribute info to handle user-only watchpoints Peter Maydell
2015-04-09 11:37 ` Edgar E. Iglesias
2015-04-07 20:10 ` [Qemu-devel] [PATCH 14/14] target-arm: Check watchpoints against CPU security state Peter Maydell
2015-04-09 11:38 ` Edgar E. Iglesias
2015-04-09 9:37 ` [Qemu-devel] [PATCH 00/14] Add memory attributes and use them in ARM Edgar E. Iglesias
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