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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Cc: "Peter Crosthwaite" <peter.crosthwaite@xilinx.com>,
	patches@linaro.org,
	"Edgar E. Iglesias" <edgar.iglesias@gmail.com>,
	"Greg Bellows" <greg.bellows@linaro.org>,
	"Paolo Bonzini" <pbonzini@redhat.com>,
	"Alex Bennée" <alex.bennee@linaro.org>,
	"Richard Henderson" <rth@twiddle.net>
Subject: [Qemu-devel] [PATCH v2 13/14] target-arm: Use attribute info to handle user-only watchpoints
Date: Mon, 13 Apr 2015 14:22:03 +0100	[thread overview]
Message-ID: <1428931324-4973-14-git-send-email-peter.maydell@linaro.org> (raw)
In-Reply-To: <1428931324-4973-1-git-send-email-peter.maydell@linaro.org>

Now that we have memory access attribute information in the watchpoint
checking code, we can correctly implement handling of watchpoints
which should match only on userspace accesses, where LDRT/STRT/LDT/STT
from EL1 are treated as userspace accesses.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
 target-arm/op_helper.c | 23 ++++++++++++-----------
 1 file changed, 12 insertions(+), 11 deletions(-)

diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c
index 7713022..4a8c4e0 100644
--- a/target-arm/op_helper.c
+++ b/target-arm/op_helper.c
@@ -602,13 +602,22 @@ static bool bp_wp_matches(ARMCPU *cpu, int n, bool is_wp)
     int pac, hmc, ssc, wt, lbn;
     /* TODO: check against CPU security state when we implement TrustZone */
     bool is_secure = false;
+    int access_el = arm_current_el(env);
 
     if (is_wp) {
-        if (!env->cpu_watchpoint[n]
-            || !(env->cpu_watchpoint[n]->flags & BP_WATCHPOINT_HIT)) {
+        CPUWatchpoint *wp = env->cpu_watchpoint[n];
+
+        if (!wp || !(wp->flags & BP_WATCHPOINT_HIT)) {
             return false;
         }
         cr = env->cp15.dbgwcr[n];
+        if (wp->hitattrs.user) {
+            /* The LDRT/STRT/LDT/STT "unprivileged access" instructions should
+             * match watchpoints as if they were accesses done at EL0, even if
+             * the CPU is at EL1 or higher.
+             */
+            access_el = 0;
+        }
     } else {
         uint64_t pc = is_a64(env) ? env->pc : env->regs[15];
 
@@ -649,15 +658,7 @@ static bool bp_wp_matches(ARMCPU *cpu, int n, bool is_wp)
         break;
     }
 
-    /* TODO: this is not strictly correct because the LDRT/STRT/LDT/STT
-     * "unprivileged access" instructions should match watchpoints as if
-     * they were accesses done at EL0, even if the CPU is at EL1 or higher.
-     * Implementing this would require reworking the core watchpoint code
-     * to plumb the mmu_idx through to this point. Luckily Linux does not
-     * rely on this behaviour currently.
-     * For breakpoints we do want to use the current CPU state.
-     */
-    switch (arm_current_el(env)) {
+    switch (access_el) {
     case 3:
     case 2:
         if (!hmc) {
-- 
1.9.1

  parent reply	other threads:[~2015-04-13 13:51 UTC|newest]

Thread overview: 35+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-04-13 13:21 [Qemu-devel] [PATCH v2 00/14] Add memory attributes and use them in ARM Peter Maydell
2015-04-13 13:21 ` [Qemu-devel] [PATCH v2 01/14] memory: Define API for MemoryRegionOps to take attrs and return status Peter Maydell
2015-04-15  1:35   ` Edgar E. Iglesias
2015-04-17 16:00   ` Alex Bennée
2015-04-13 13:21 ` [Qemu-devel] [PATCH v2 02/14] memory: Replace io_mem_read/write with memory_region_dispatch_read/write Peter Maydell
2015-04-17 16:01   ` Alex Bennée
2015-04-13 13:21 ` [Qemu-devel] [PATCH v2 03/14] Make CPU iotlb a structure rather than a plain hwaddr Peter Maydell
2015-04-17 16:08   ` Alex Bennée
2015-04-13 13:21 ` [Qemu-devel] [PATCH v2 04/14] Add MemTxAttrs to the IOTLB Peter Maydell
2015-04-17 16:09   ` Alex Bennée
2015-04-13 13:21 ` [Qemu-devel] [PATCH v2 05/14] exec.c: Convert subpage memory ops to _with_attrs Peter Maydell
2015-04-17 16:15   ` Alex Bennée
2015-04-17 16:18     ` Peter Maydell
2015-04-17 16:25       ` Alex Bennée
2015-04-13 13:21 ` [Qemu-devel] [PATCH v2 06/14] exec.c: Make address_space_rw take transaction attributes Peter Maydell
2015-04-21  7:39   ` Alex Bennée
2015-04-21 13:27     ` Peter Maydell
2015-04-13 13:21 ` [Qemu-devel] [PATCH v2 07/14] exec.c: Add new address_space_ld*/st* functions Peter Maydell
2015-04-21  8:36   ` Alex Bennée
2015-04-13 13:21 ` [Qemu-devel] [PATCH v2 08/14] exec.c: Capture the memory attributes for a watchpoint hit Peter Maydell
2015-04-21  8:42   ` Alex Bennée
2015-04-13 13:21 ` [Qemu-devel] [PATCH v2 09/14] Switch non-CPU callers from ld/st*_phys to address_space_ld/st* Peter Maydell
2015-04-21  8:44   ` Alex Bennée
2015-04-13 13:22 ` [Qemu-devel] [PATCH v2 10/14] target-arm: Honour NS bits in page tables Peter Maydell
2015-04-21  9:24   ` Alex Bennée
2015-04-21 13:28     ` Peter Maydell
2015-04-13 13:22 ` [Qemu-devel] [PATCH v2 11/14] target-arm: Use correct memory attributes for page table walks Peter Maydell
2015-04-21  9:36   ` Alex Bennée
2015-04-13 13:22 ` [Qemu-devel] [PATCH v2 12/14] target-arm: Add user-mode transaction attribute Peter Maydell
2015-04-21  9:36   ` Alex Bennée
2015-04-13 13:22 ` Peter Maydell [this message]
2015-04-21  9:37   ` [Qemu-devel] [PATCH v2 13/14] target-arm: Use attribute info to handle user-only watchpoints Alex Bennée
2015-04-13 13:22 ` [Qemu-devel] [PATCH v2 14/14] target-arm: Check watchpoints against CPU security state Peter Maydell
2015-04-21  9:37   ` Alex Bennée
2015-04-21 13:35 ` [Qemu-devel] [PATCH v2 00/14] Add memory attributes and use them in ARM Peter Maydell

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