* [Qemu-devel] [PATCH] target-arm: Adjust id_aa64pfr0 when has_el3 CPU property disabled
@ 2015-04-22 2:18 Sergey Fedorov
2015-04-22 14:04 ` Greg Bellows
2015-04-23 12:25 ` Peter Maydell
0 siblings, 2 replies; 3+ messages in thread
From: Sergey Fedorov @ 2015-04-22 2:18 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell, Sergey Fedorov
Signed-off-by: Sergey Fedorov <serge.fdrv@gmail.com>
---
target-arm/cpu.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index 986f04c..327b1e5 100644
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -524,9 +524,10 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
unset_feature(env, ARM_FEATURE_EL3);
/* Disable the security extension feature bits in the processor feature
- * register as well. This is id_pfr1[7:4].
+ * registers as well. These are id_pfr1[7:4] and id_aa64pfr0[15:12].
*/
cpu->id_pfr1 &= ~0xf0;
+ cpu->id_aa64pfr0 &= ~0xf000;
}
register_cp_regs_for_features(cpu);
--
2.3.4
^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [Qemu-devel] [PATCH] target-arm: Adjust id_aa64pfr0 when has_el3 CPU property disabled
2015-04-22 2:18 [Qemu-devel] [PATCH] target-arm: Adjust id_aa64pfr0 when has_el3 CPU property disabled Sergey Fedorov
@ 2015-04-22 14:04 ` Greg Bellows
2015-04-23 12:25 ` Peter Maydell
1 sibling, 0 replies; 3+ messages in thread
From: Greg Bellows @ 2015-04-22 14:04 UTC (permalink / raw)
To: Sergey Fedorov; +Cc: Peter Maydell, QEMU Developers
[-- Attachment #1: Type: text/plain, Size: 970 bytes --]
On Tue, Apr 21, 2015 at 9:18 PM, Sergey Fedorov <serge.fdrv@gmail.com>
wrote:
> Signed-off-by: Sergey Fedorov <serge.fdrv@gmail.com>
> ---
> target-arm/cpu.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/target-arm/cpu.c b/target-arm/cpu.c
> index 986f04c..327b1e5 100644
> --- a/target-arm/cpu.c
> +++ b/target-arm/cpu.c
> @@ -524,9 +524,10 @@ static void arm_cpu_realizefn(DeviceState *dev, Error
> **errp)
> unset_feature(env, ARM_FEATURE_EL3);
>
> /* Disable the security extension feature bits in the processor
> feature
> - * register as well. This is id_pfr1[7:4].
> + * registers as well. These are id_pfr1[7:4] and
> id_aa64pfr0[15:12].
> */
> cpu->id_pfr1 &= ~0xf0;
> + cpu->id_aa64pfr0 &= ~0xf000;
> }
>
> register_cp_regs_for_features(cpu);
> --
> 2.3.4
>
>
> Reviewed-by: Greg Bellows <greg.bellows@linaro.org>
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^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [Qemu-devel] [PATCH] target-arm: Adjust id_aa64pfr0 when has_el3 CPU property disabled
2015-04-22 2:18 [Qemu-devel] [PATCH] target-arm: Adjust id_aa64pfr0 when has_el3 CPU property disabled Sergey Fedorov
2015-04-22 14:04 ` Greg Bellows
@ 2015-04-23 12:25 ` Peter Maydell
1 sibling, 0 replies; 3+ messages in thread
From: Peter Maydell @ 2015-04-23 12:25 UTC (permalink / raw)
To: Sergey Fedorov; +Cc: QEMU Developers
On 22 April 2015 at 03:18, Sergey Fedorov <serge.fdrv@gmail.com> wrote:
> Signed-off-by: Sergey Fedorov <serge.fdrv@gmail.com>
> ---
> target-arm/cpu.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
Applied to target-arm.next, thanks.
-- PMM
^ permalink raw reply [flat|nested] 3+ messages in thread
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2015-04-22 2:18 [Qemu-devel] [PATCH] target-arm: Adjust id_aa64pfr0 when has_el3 CPU property disabled Sergey Fedorov
2015-04-22 14:04 ` Greg Bellows
2015-04-23 12:25 ` Peter Maydell
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