From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42033) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Yky9k-0007LL-1P for qemu-devel@nongnu.org; Wed, 22 Apr 2015 13:09:48 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Yky9f-0004ro-Uy for qemu-devel@nongnu.org; Wed, 22 Apr 2015 13:09:47 -0400 Received: from mail-oi0-f52.google.com ([209.85.218.52]:36673) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Yky9f-0004rY-RT for qemu-devel@nongnu.org; Wed, 22 Apr 2015 13:09:43 -0400 Received: by oift201 with SMTP id t201so186214964oif.3 for ; Wed, 22 Apr 2015 10:09:43 -0700 (PDT) From: Greg Bellows Date: Wed, 22 Apr 2015 12:09:18 -0500 Message-Id: <1429722561-12651-7-git-send-email-greg.bellows@linaro.org> In-Reply-To: <1429722561-12651-1-git-send-email-greg.bellows@linaro.org> References: <1429722561-12651-1-git-send-email-greg.bellows@linaro.org> Subject: [Qemu-devel] [PATCH v2 6/9] target-arm: Add TTBR regime function and use List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org, peter.maydell@linaro.org, alex.bennee@linaro.org Cc: serge.fdrv@gmail.com, Greg Bellows Add a utility function for choosing the correct TTBR system register based on the specified MMU index. Add use of function on physical address lookup. Signed-off-by: Greg Bellows --- target-arm/helper.c | 24 +++++++++++++++++++----- 1 file changed, 19 insertions(+), 5 deletions(-) diff --git a/target-arm/helper.c b/target-arm/helper.c index e36c3d4..69a5891 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -4899,6 +4899,21 @@ static inline TCR *regime_tcr(CPUARMState *env, ARMMMUIdx mmu_idx) return &env->cp15.tcr_el[regime_el(env, mmu_idx)]; } +/* Return the TTBR associated with this translation regime */ +static inline uint32_t regime_ttbr(CPUARMState *env, ARMMMUIdx mmu_idx, + int ttbrn) +{ + if (mmu_idx == ARMMMUIdx_S2NS) { + /* TODO: return VTTBR_EL2 */ + g_assert_not_reached(); + } + if (ttbrn == 0) { + return env->cp15.ttbr0_el[regime_el(env, mmu_idx)]; + } else { + return env->cp15.ttbr1_el[regime_el(env, mmu_idx)]; + } +} + /* Return true if the translation regime is using LPAE format page tables */ static inline bool regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx) @@ -5097,7 +5112,6 @@ static bool get_level1_table_address(CPUARMState *env, ARMMMUIdx mmu_idx, uint32_t *table, uint32_t address) { /* Note that we can only get here for an AArch32 PL0/PL1 lookup */ - int el = regime_el(env, mmu_idx); TCR *tcr = regime_tcr(env, mmu_idx); if (address & tcr->mask) { @@ -5105,13 +5119,13 @@ static bool get_level1_table_address(CPUARMState *env, ARMMMUIdx mmu_idx, /* Translation table walk disabled for TTBR1 */ return false; } - *table = env->cp15.ttbr1_el[el] & 0xffffc000; + *table = regime_ttbr(env, mmu_idx, 1) & 0xffffc000; } else { if (tcr->raw_tcr & TTBCR_PD0) { /* Translation table walk disabled for TTBR0 */ return false; } - *table = env->cp15.ttbr0_el[el] & tcr->base_mask; + *table = regime_ttbr(env, mmu_idx, 0) & tcr->base_mask; } *table |= (address >> 18) & 0x3ffc; return true; @@ -5441,7 +5455,7 @@ static int get_phys_addr_lpae(CPUARMState *env, target_ulong address, * we will always flush the TLB any time the ASID is changed). */ if (ttbr_select == 0) { - ttbr = A32_BANKED_CURRENT_REG_GET(env, ttbr0); + ttbr = regime_ttbr(env, mmu_idx, 0); epd = extract32(tcr->raw_tcr, 7, 1); tsz = t0sz; @@ -5453,7 +5467,7 @@ static int get_phys_addr_lpae(CPUARMState *env, target_ulong address, granule_sz = 11; } } else { - ttbr = A32_BANKED_CURRENT_REG_GET(env, ttbr1); + ttbr = regime_ttbr(env, mmu_idx, 1); epd = extract32(tcr->raw_tcr, 23, 1); tsz = t1sz; -- 1.8.3.2