From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37764) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Ymkq8-0004AY-Ff for qemu-devel@nongnu.org; Mon, 27 Apr 2015 11:20:57 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Ymkq6-0003Zz-4o for qemu-devel@nongnu.org; Mon, 27 Apr 2015 11:20:56 -0400 Received: from mnementh.archaic.org.uk ([2001:8b0:1d0::1]:34016) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Ymkq5-0003Ym-UG for qemu-devel@nongnu.org; Mon, 27 Apr 2015 11:20:54 -0400 Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.80) (envelope-from ) id 1Ymkpy-0008SK-AS for qemu-devel@nongnu.org; Mon, 27 Apr 2015 16:20:46 +0100 From: Peter Maydell Date: Mon, 27 Apr 2015 16:20:44 +0100 Message-Id: <1430148045-32400-17-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1430148045-32400-1-git-send-email-peter.maydell@linaro.org> References: <1430148045-32400-1-git-send-email-peter.maydell@linaro.org> Subject: [Qemu-devel] [PULL 16/17] target-arm: Adjust id_aa64pfr0 when has_el3 CPU property disabled List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org From: Sergey Fedorov Signed-off-by: Sergey Fedorov Message-id: 1429669112-29835-1-git-send-email-serge.fdrv@gmail.com Reviewed-by: Greg Bellows Signed-off-by: Peter Maydell --- target-arm/cpu.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/target-arm/cpu.c b/target-arm/cpu.c index 3b5a93d..3ca3fa8 100644 --- a/target-arm/cpu.c +++ b/target-arm/cpu.c @@ -524,9 +524,10 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) unset_feature(env, ARM_FEATURE_EL3); /* Disable the security extension feature bits in the processor feature - * register as well. This is id_pfr1[7:4]. + * registers as well. These are id_pfr1[7:4] and id_aa64pfr0[15:12]. */ cpu->id_pfr1 &= ~0xf0; + cpu->id_aa64pfr0 &= ~0xf000; } register_cp_regs_for_features(cpu); -- 1.9.1