From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46661) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Yn4pq-00062d-P3 for qemu-devel@nongnu.org; Tue, 28 Apr 2015 08:42:01 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Yn4pp-0005sP-FT for qemu-devel@nongnu.org; Tue, 28 Apr 2015 08:41:58 -0400 Received: from mailapp01.imgtec.com ([195.59.15.196]:7799) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Yn4pp-0005sI-A7 for qemu-devel@nongnu.org; Tue, 28 Apr 2015 08:41:57 -0400 From: Leon Alrae Date: Tue, 28 Apr 2015 13:41:12 +0100 Message-ID: <1430224874-18513-6-git-send-email-leon.alrae@imgtec.com> In-Reply-To: <1430224874-18513-1-git-send-email-leon.alrae@imgtec.com> References: <1430224874-18513-1-git-send-email-leon.alrae@imgtec.com> MIME-Version: 1.0 Content-Type: text/plain Subject: [Qemu-devel] [PATCH 5/7] target-mips: correct MFC0 for CP0.EntryLo in MIPS64 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: aurelien@aurel32.net Since PFNX is now supported the bits 31:30 have to be cleared. Signed-off-by: Leon Alrae --- target-mips/translate.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/target-mips/translate.c b/target-mips/translate.c index f95b655..a41fc98 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -5144,10 +5144,10 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel) tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EntryLo0)); #if defined(TARGET_MIPS64) if (ctx->rxi) { + /* Move RI/XI fields to bits 31:30 */ TCGv tmp = tcg_temp_new(); - tcg_gen_andi_tl(tmp, arg, (3ull << CP0EnLo_XI)); - tcg_gen_shri_tl(tmp, tmp, 32); - tcg_gen_or_tl(arg, arg, tmp); + tcg_gen_shri_tl(tmp, arg, CP0EnLo_XI); + tcg_gen_deposit_tl(arg, arg, tmp, 30, 2); tcg_temp_free(tmp); } #endif @@ -5199,10 +5199,10 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel) tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EntryLo1)); #if defined(TARGET_MIPS64) if (ctx->rxi) { + /* Move RI/XI fields to bits 31:30 */ TCGv tmp = tcg_temp_new(); - tcg_gen_andi_tl(tmp, arg, (3ull << CP0EnLo_XI)); - tcg_gen_shri_tl(tmp, tmp, 32); - tcg_gen_or_tl(arg, arg, tmp); + tcg_gen_shri_tl(tmp, arg, CP0EnLo_XI); + tcg_gen_deposit_tl(arg, arg, tmp, 30, 2); tcg_temp_free(tmp); } #endif