From: Leon Alrae <leon.alrae@imgtec.com>
To: qemu-devel@nongnu.org
Cc: aurelien@aurel32.net
Subject: [Qemu-devel] [PATCH 6/7] target-mips: remove invalid comments in translate_init.c
Date: Tue, 28 Apr 2015 13:41:13 +0100 [thread overview]
Message-ID: <1430224874-18513-7-git-send-email-leon.alrae@imgtec.com> (raw)
In-Reply-To: <1430224874-18513-1-git-send-email-leon.alrae@imgtec.com>
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
---
target-mips/translate_init.c | 9 ---------
1 file changed, 9 deletions(-)
diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c
index 8e088c9..af6fb7a 100644
--- a/target-mips/translate_init.c
+++ b/target-mips/translate_init.c
@@ -553,9 +553,6 @@ static const mips_def_t mips_defs[] =
(1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
(1 << FCR0_S) | (0x00 << FCR0_PRID) | (0x0 << FCR0_REV),
.SEGBITS = 42,
- /* The architectural limit is 59, but we have hardcoded 36 bit
- in some places...
- .PABITS = 59, */ /* the architectural limit */
.PABITS = 36,
.insn_flags = CPU_MIPS64R2 | ASE_MIPS3D,
.mmu_type = MMU_TYPE_R4000,
@@ -636,9 +633,6 @@ static const mips_def_t mips_defs[] =
(1 << FCR0_W) | (1 << FCR0_D) | (1 << FCR0_S) |
(0x00 << FCR0_PRID) | (0x0 << FCR0_REV),
.SEGBITS = 42,
- /* The architectural limit is 59, but we have hardcoded 36 bit
- in some places...
- .PABITS = 59, */ /* the architectural limit */
.PABITS = 36,
.insn_flags = CPU_MIPS64R6,
.mmu_type = MMU_TYPE_R4000,
@@ -702,9 +696,6 @@ static const mips_def_t mips_defs[] =
(1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
(1 << FCR0_S) | (0x00 << FCR0_PRID) | (0x0 << FCR0_REV),
.SEGBITS = 42,
- /* The architectural limit is 59, but we have hardcoded 36 bit
- in some places...
- .PABITS = 59, */ /* the architectural limit */
.PABITS = 36,
.insn_flags = CPU_MIPS64R2 | ASE_DSP | ASE_DSPR2,
.mmu_type = MMU_TYPE_R4000,
next prev parent reply other threads:[~2015-04-28 12:42 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-04-28 12:41 [Qemu-devel] [PATCH 0/7] target-mips: add support for large physical addresses Leon Alrae
2015-04-28 12:41 ` [Qemu-devel] [PATCH 1/7] target-mips: extend selected CP0 registers to 64-bits in MIPS32 Leon Alrae
2015-04-28 12:41 ` [Qemu-devel] [PATCH 2/7] target-mips: support Page Frame Number Extension field Leon Alrae
2015-04-28 13:35 ` James Hogan
2015-04-28 13:47 ` James Hogan
2015-04-28 15:59 ` Leon Alrae
2015-04-28 21:39 ` James Hogan
2015-04-29 15:31 ` Leon Alrae
2015-04-28 12:41 ` [Qemu-devel] [PATCH 3/7] target-mips: add CP0.PageGrain.ELPA support Leon Alrae
2015-04-28 15:08 ` James Hogan
2015-04-29 11:35 ` Leon Alrae
2015-04-28 12:41 ` [Qemu-devel] [PATCH 4/7] target-mips: add MTHC0 and MFHC0 instructions Leon Alrae
2015-04-28 15:52 ` James Hogan
2015-04-29 14:26 ` Leon Alrae
2015-04-28 12:41 ` [Qemu-devel] [PATCH 5/7] target-mips: correct MFC0 for CP0.EntryLo in MIPS64 Leon Alrae
2015-04-28 12:41 ` Leon Alrae [this message]
2015-04-28 21:50 ` [Qemu-devel] [PATCH 6/7] target-mips: remove invalid comments in translate_init.c James Hogan
2015-04-28 12:41 ` [Qemu-devel] [PATCH 7/7] target-mips: enable XPA and LPA features Leon Alrae
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