From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58730) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Yn6hK-00084A-US for qemu-devel@nongnu.org; Tue, 28 Apr 2015 10:41:22 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Yn6hG-0001DL-2i for qemu-devel@nongnu.org; Tue, 28 Apr 2015 10:41:18 -0400 Received: from mx1.redhat.com ([209.132.183.28]:48754) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Yn6hF-0001Cu-U6 for qemu-devel@nongnu.org; Tue, 28 Apr 2015 10:41:14 -0400 From: Paolo Bonzini Date: Tue, 28 Apr 2015 16:40:27 +0200 Message-Id: <1430232029-9457-21-git-send-email-pbonzini@redhat.com> In-Reply-To: <1430232029-9457-1-git-send-email-pbonzini@redhat.com> References: <1430232029-9457-1-git-send-email-pbonzini@redhat.com> Subject: [Qemu-devel] [PULL 20/22] target-i386: disable LINT0 after reset List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Nadav Amit From: Nadav Amit Due to old Seabios bug, QEMU reenable LINT0 after reset. This bug is long gone and therefore this hack is no longer needed. Since it violates the specifications, it is removed. Signed-off-by: Nadav Amit Message-Id: <1428881529-29459-2-git-send-email-namit@cs.technion.ac.il> Signed-off-by: Paolo Bonzini --- hw/intc/apic_common.c | 9 --------- 1 file changed, 9 deletions(-) diff --git a/hw/intc/apic_common.c b/hw/intc/apic_common.c index 042e960..d38d24b 100644 --- a/hw/intc/apic_common.c +++ b/hw/intc/apic_common.c @@ -243,15 +243,6 @@ static void apic_reset_common(DeviceState *dev) info->vapic_base_update(s); apic_init_reset(dev); - - if (bsp) { - /* - * LINT0 delivery mode on CPU #0 is set to ExtInt at initialization - * time typically by BIOS, so PIC interrupt can be delivered to the - * processor when local APIC is enabled. - */ - s->lvt[APIC_LVT_LINT0] = 0x700; - } } /* This function is only used for old state version 1 and 2 */ -- 2.3.5