From: Christopher Covington <christopher.covington@linaro.org>
To: peter.maydell@linaro.org, qemu-devel@nongnu.org
Cc: Christopher Covington <christopher.covington@linaro.org>
Subject: [Qemu-devel] [RFC 1/5] arm64: Add PMINTENCLR_EL1
Date: Thu, 30 Apr 2015 14:14:23 -0400 [thread overview]
Message-ID: <1430417667-4245-1-git-send-email-christopher.covington@linaro.org> (raw)
The Linux kernel accesses this register early in its setup.
Signed-off-by: Christopher Covington <christopher.covington@linaro.org>
---
target-arm/helper.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index d77c6de..6aeb77c 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -954,6 +954,11 @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
.access = PL1_RW, .type = ARM_CP_ALIAS,
.fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
.resetvalue = 0, .writefn = pmintenclr_write, },
+ { .name = "PMINTENCLR_EL1", .state = ARM_CP_STATE_AA64,
+ .opc0 = 3, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 2,
+ .access = PL1_RW, .type = ARM_CP_ALIAS,
+ .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
+ .resetvalue = 0, .writefn = pmintenclr_write, },
{ .name = "VBAR", .state = ARM_CP_STATE_BOTH,
.opc0 = 3, .crn = 12, .crm = 0, .opc1 = 0, .opc2 = 0,
.access = PL1_RW, .writefn = vbar_write,
--
1.9.1
next reply other threads:[~2015-04-30 18:15 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-04-30 18:14 Christopher Covington [this message]
2015-04-30 18:14 ` [Qemu-devel] [RFC 2/5] arm64: Add PMOVSCLR_EL0 register Christopher Covington
2015-04-30 18:14 ` [Qemu-devel] [RFC 3/5] arm64: Add PMUSERENR_EL0 register Christopher Covington
2015-04-30 18:14 ` [Qemu-devel] [RFC 4/5] arm64: Unmask PMU bits in debug feature register Christopher Covington
2015-04-30 18:14 ` [Qemu-devel] [RFC 5/5] arm: Simplify cycle counter Christopher Covington
2015-04-30 18:27 ` Peter Maydell
2015-04-30 21:33 ` Christopher Covington
2015-04-30 22:02 ` Peter Maydell
2015-05-04 9:54 ` Paolo Bonzini
2015-05-01 1:24 ` Peter Crosthwaite
2015-05-01 14:35 ` Christopher Covington
2015-05-06 14:05 ` Peter Crosthwaite
2015-05-06 15:38 ` Peter Maydell
2015-09-24 19:43 ` [Qemu-devel] [PATCH] target-arm: Use common CPU cycle infrastructure Christopher Covington
2015-09-28 22:05 ` Alistair Francis
2015-09-29 14:07 ` Christopher Covington
2015-10-02 16:44 ` Christopher Covington
2015-10-02 16:56 ` Peter Maydell
2015-10-02 17:25 ` Peter Crosthwaite
2015-10-02 18:08 ` Peter Maydell
2015-10-02 18:14 ` Peter Crosthwaite
2015-10-02 19:25 ` Christopher Covington
2015-10-02 19:56 ` Peter Crosthwaite
2015-10-02 20:48 ` Christopher Covington
2015-10-02 22:41 ` Peter Maydell
2015-10-05 14:09 ` Paolo Bonzini
2015-10-05 14:11 ` Peter Maydell
2015-10-05 14:27 ` Paolo Bonzini
2015-10-06 12:49 ` Peter Maydell
2015-10-06 12:58 ` Paolo Bonzini
2015-10-06 13:06 ` Peter Maydell
2015-10-06 13:10 ` Paolo Bonzini
2015-10-13 20:53 ` Peter Maydell
2015-10-14 12:10 ` Christopher Covington
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