From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38414) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YnszI-0003J3-A8 for qemu-devel@nongnu.org; Thu, 30 Apr 2015 14:15:05 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YnszD-0001sE-5G for qemu-devel@nongnu.org; Thu, 30 Apr 2015 14:15:04 -0400 Received: from mail-pd0-f173.google.com ([209.85.192.173]:34144) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YnszC-0001rr-Ve for qemu-devel@nongnu.org; Thu, 30 Apr 2015 14:14:59 -0400 Received: by pdbqa5 with SMTP id qa5so68093930pdb.1 for ; Thu, 30 Apr 2015 11:14:57 -0700 (PDT) From: Christopher Covington Date: Thu, 30 Apr 2015 14:14:23 -0400 Message-Id: <1430417667-4245-1-git-send-email-christopher.covington@linaro.org> Subject: [Qemu-devel] [RFC 1/5] arm64: Add PMINTENCLR_EL1 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: peter.maydell@linaro.org, qemu-devel@nongnu.org Cc: Christopher Covington The Linux kernel accesses this register early in its setup. Signed-off-by: Christopher Covington --- target-arm/helper.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/target-arm/helper.c b/target-arm/helper.c index d77c6de..6aeb77c 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -954,6 +954,11 @@ static const ARMCPRegInfo v7_cp_reginfo[] = { .access = PL1_RW, .type = ARM_CP_ALIAS, .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten), .resetvalue = 0, .writefn = pmintenclr_write, }, + { .name = "PMINTENCLR_EL1", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 2, + .access = PL1_RW, .type = ARM_CP_ALIAS, + .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten), + .resetvalue = 0, .writefn = pmintenclr_write, }, { .name = "VBAR", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .crn = 12, .crm = 0, .opc1 = 0, .opc2 = 0, .access = PL1_RW, .writefn = vbar_write, -- 1.9.1