From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38492) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YnszU-0003d2-GH for qemu-devel@nongnu.org; Thu, 30 Apr 2015 14:15:24 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YnszN-0002Aw-55 for qemu-devel@nongnu.org; Thu, 30 Apr 2015 14:15:16 -0400 Received: from mail-pd0-f181.google.com ([209.85.192.181]:34398) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YnszN-0002An-0q for qemu-devel@nongnu.org; Thu, 30 Apr 2015 14:15:09 -0400 Received: by pdbqa5 with SMTP id qa5so68098776pdb.1 for ; Thu, 30 Apr 2015 11:15:08 -0700 (PDT) From: Christopher Covington Date: Thu, 30 Apr 2015 14:14:26 -0400 Message-Id: <1430417667-4245-4-git-send-email-christopher.covington@linaro.org> In-Reply-To: <1430417667-4245-1-git-send-email-christopher.covington@linaro.org> References: <1430417667-4245-1-git-send-email-christopher.covington@linaro.org> Subject: [Qemu-devel] [RFC 4/5] arm64: Unmask PMU bits in debug feature register List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: peter.maydell@linaro.org, qemu-devel@nongnu.org Cc: Christopher Covington The previously missing registers are now present in QEMU. Signed-off-by: Christopher Covington --- target-arm/helper.c | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/target-arm/helper.c b/target-arm/helper.c index 863cfd0..3e6fb0b 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -3149,12 +3149,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) { .name = "ID_AA64DFR0_EL1", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 0, .access = PL1_R, .type = ARM_CP_CONST, - /* We mask out the PMUVer field, because we don't currently - * implement the PMU. Not advertising it prevents the guest - * from trying to use it and getting UNDEFs on registers we - * don't implement. - */ - .resetvalue = cpu->id_aa64dfr0 & ~0xf00 }, + .resetvalue = cpu->id_aa64dfr0 }, { .name = "ID_AA64DFR1_EL1", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 1, .access = PL1_R, .type = ARM_CP_CONST, -- 1.9.1