From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38509) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YnszV-0003fO-UL for qemu-devel@nongnu.org; Thu, 30 Apr 2015 14:15:19 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YnszQ-0002Bn-VB for qemu-devel@nongnu.org; Thu, 30 Apr 2015 14:15:17 -0400 Received: from mail-pa0-f41.google.com ([209.85.220.41]:35530) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YnszQ-0002Bj-QT for qemu-devel@nongnu.org; Thu, 30 Apr 2015 14:15:12 -0400 Received: by pabtp1 with SMTP id tp1so67028659pab.2 for ; Thu, 30 Apr 2015 11:15:12 -0700 (PDT) From: Christopher Covington Date: Thu, 30 Apr 2015 14:14:27 -0400 Message-Id: <1430417667-4245-5-git-send-email-christopher.covington@linaro.org> In-Reply-To: <1430417667-4245-1-git-send-email-christopher.covington@linaro.org> References: <1430417667-4245-1-git-send-email-christopher.covington@linaro.org> Subject: [Qemu-devel] [RFC 5/5] arm: Simplify cycle counter List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: peter.maydell@linaro.org, qemu-devel@nongnu.org Cc: Christopher Covington Present a system with an instructions per cycle of exactly one. This makes it less likely a user will mistake the cycle counter values as meaningful and makes calculations involving cycles trivial while preserving the necessary property of the cycle counter register as monotonically increasing. Signed-off-by: Christopher Covington --- target-arm/helper.c | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/target-arm/helper.c b/target-arm/helper.c index 3e6fb0b..a027a19 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -648,8 +648,7 @@ void pmccntr_sync(CPUARMState *env) { uint64_t temp_ticks; - temp_ticks = muldiv64(qemu_clock_get_us(QEMU_CLOCK_VIRTUAL), - get_ticks_per_sec(), 1000000); + temp_ticks = cpu_get_icount_raw(); if (env->cp15.c9_pmcr & PMCRD) { /* Increment once every 64 processor clock cycles */ @@ -687,8 +686,7 @@ static uint64_t pmccntr_read(CPUARMState *env, const ARMCPRegInfo *ri) return env->cp15.c15_ccnt; } - total_ticks = muldiv64(qemu_clock_get_us(QEMU_CLOCK_VIRTUAL), - get_ticks_per_sec(), 1000000); + total_ticks = cpu_get_icount_raw(); if (env->cp15.c9_pmcr & PMCRD) { /* Increment once every 64 processor clock cycles */ @@ -708,8 +706,7 @@ static void pmccntr_write(CPUARMState *env, const ARMCPRegInfo *ri, return; } - total_ticks = muldiv64(qemu_clock_get_us(QEMU_CLOCK_VIRTUAL), - get_ticks_per_sec(), 1000000); + total_ticks = cpu_get_icount_raw(); if (env->cp15.c9_pmcr & PMCRD) { /* Increment once every 64 processor clock cycles */ -- 1.9.1