From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53884) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YnwNS-00010Y-Af for qemu-devel@nongnu.org; Thu, 30 Apr 2015 17:52:15 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YnwNP-0002hF-5c for qemu-devel@nongnu.org; Thu, 30 Apr 2015 17:52:14 -0400 Received: from mail-pa0-x22b.google.com ([2607:f8b0:400e:c03::22b]:35992) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YnwNO-0002h3-UX for qemu-devel@nongnu.org; Thu, 30 Apr 2015 17:52:11 -0400 Received: by pabsx10 with SMTP id sx10so72061982pab.3 for ; Thu, 30 Apr 2015 14:52:10 -0700 (PDT) From: James Sullivan Date: Thu, 30 Apr 2015 15:49:12 -0600 Message-Id: <1430430556-21869-1-git-send-email-sullivan.james.f@gmail.com> Subject: [Qemu-devel] [PATCH v3 0/4] apic: Implement MSI RH bit handling, lowpri IRQ delivery List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: pbonzini@redhat.com, James Sullivan , jan.kiszka@siemens.com Changes in v2: * Merged in low priority IRQ delivery implementation to RH bit handling implementation, since both rely on the same helper functions for priority arbitration. * Corrected use of MSI data register => addr register when setting msi_redir_hint in apic_send_msi(). Changes in v3: * Fixed apic_get_arb_pri() to match the algorithm outlined in the AMD manual vs. the (incorrect?) Intel manual. * Removed apic_lowest_prio() in favour of performing the arbitration within apic_get_delivery_bitmask() while we iterate through the LAPICs (saves a few calls to an iteration over all LAPICs). * Modified delivery of APIC_DM_LOWPRI to be identical to APIC_DM_FIXED (since we account for arbitration when setting the delivery bitmask) This set of patches adds the following features to QEMU: * Low priority delivery arbitration. Currently the first present CPU is always selected when lowpri delivery mode is used, and no arbitration is performed. Implemented arbitration in apic_bus_deliver() by adding the following functions: 1) apic_get_arb_pri(APICCommonState *s) 2) apic_compare_prio(APICCommonState *s1, APICCommonState *s2); 3) apic_lowest_prio(const uint32_t *deliver_bitmask) * RH Bit handling for MSI messages. See below. Currently, there is no handling of the MSI RH bit. This patch implements the following logic: * DM=0, RH=* : Physical destination mode. Interrupt is delivered to the LAPIC with the matching APIC ID. (Subject to the usual restrictions, i.e. no broadcast dest) * DM=1, RH=0 : Logical destination mode without redirection. Interrupt is delivered to all LAPICs in the logical group specified by the IRQ's destination map and delivery mode. * DM=1, RH=1 : Logical destination mode with redirection. Interrupt is delivered only to the lowest priority LAPIC in the logical group specified by the dest map and the delivery mode. Delivery semantics are otherwise specified by the delivery_mode of the IRQ, which is unchanged. These changes reflect those made in the KVM in http://www.spinics.net/lists/kvm/msg114915.html ("kvm: x86: Implement handling of RH=1 for MSI delivery in KVM"), which is queued for 4.2. James Sullivan (4): apic: Implement LAPIC low priority arbitration functions apic: Set and pass in RH bit for MSI interrupts apic: Add helper functions apic_match_dest, apic_match_[physical,logical]_dest apic: Handle RH=1 and lowpri delivery mode in apic_get_delivery_bitmask() hw/intc/apic.c | 130 ++++++++++++++++++++++++++++++++----------------- hw/intc/ioapic.c | 2 +- include/hw/i386/apic.h | 3 +- trace-events | 2 +- 4 files changed, 90 insertions(+), 47 deletions(-) -- 2.3.5