From: James Sullivan <sullivan.james.f@gmail.com>
To: qemu-devel@nongnu.org
Cc: pbonzini@redhat.com, James Sullivan <sullivan.james.f@gmail.com>,
jan.kiszka@siemens.com
Subject: [Qemu-devel] [PATCH v3 1/4] apic: Implement LAPIC low priority arbitration functions
Date: Thu, 30 Apr 2015 15:49:13 -0600 [thread overview]
Message-ID: <1430430556-21869-2-git-send-email-sullivan.james.f@gmail.com> (raw)
In-Reply-To: <1430430556-21869-1-git-send-email-sullivan.james.f@gmail.com>
Currently, apic_get_arb_pri() is unimplemented and returns 0.
Implemented apic_get_arb_pri() and added helper function
apic_compare_prio() to be used for LAPIC arbitration.
Signed-off-by: James Sullivan <sullivan.james.f@gmail.com>
---
Changes in v3:
* Fixed apic_get_arb_pri to use AMD's algorithm vs. Intel's
(incorrect?) algorithm
* Removed apic_lowest_prio() in favour of arbitration while setting
up the delivery bitmask (added in 4/4)
hw/intc/apic.c | 30 ++++++++++++++++++++++++++++--
1 file changed, 28 insertions(+), 2 deletions(-)
diff --git a/hw/intc/apic.c b/hw/intc/apic.c
index 0f97b47..8f6cdd2 100644
--- a/hw/intc/apic.c
+++ b/hw/intc/apic.c
@@ -38,6 +38,7 @@ static void apic_set_irq(APICCommonState *s, int vector_num, int trigger_mode);
static void apic_update_irq(APICCommonState *s);
static void apic_get_delivery_bitmask(uint32_t *deliver_bitmask,
uint8_t dest, uint8_t dest_mode);
+static int apic_get_arb_pri(APICCommonState *s);
/* Find first bit starting from msb */
static int apic_fls_bit(uint32_t value)
@@ -217,6 +218,12 @@ static void apic_external_nmi(APICCommonState *s)
}\
}
+static int apic_compare_prio(struct APICCommonState *cpu1,
+ struct APICCommonState *cpu2)
+{
+ return apic_get_arb_pri(cpu1) - apic_get_arb_pri(cpu2);
+}
+
static void apic_bus_deliver(const uint32_t *deliver_bitmask,
uint8_t delivery_mode, uint8_t vector_num,
uint8_t trigger_mode)
@@ -336,8 +343,27 @@ static int apic_get_ppr(APICCommonState *s)
static int apic_get_arb_pri(APICCommonState *s)
{
- /* XXX: arbitration */
- return 0;
+ int tpr, isrv, irrv, apr;
+
+ tpr = apic_get_tpr(s);
+ isrv = get_highest_priority_int(s->isr);
+ if (isrv < 0) {
+ isrv = 0;
+ }
+ isrv >>= 4;
+ irrv = get_highest_priority_int(s->irr);
+ if (irrv < 0) {
+ irrv = 0;
+ }
+ irrv >>= 4;
+
+ if ((tpr >= irrv) && (tpr > isrv)) {
+ apr = s->tpr & 0xff;
+ } else {
+ apr = (isrv > irrv) ? isrv : irrv;
+ apr <<= 4;
+ }
+ return apr;
}
--
2.3.5
next prev parent reply other threads:[~2015-04-30 21:52 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-04-30 21:49 [Qemu-devel] [PATCH v3 0/4] apic: Implement MSI RH bit handling, lowpri IRQ delivery James Sullivan
2015-04-30 21:49 ` James Sullivan [this message]
2015-04-30 21:49 ` [Qemu-devel] [PATCH v3 2/4] apic: Set and pass in RH bit for MSI interrupts James Sullivan
2015-04-30 21:49 ` [Qemu-devel] [PATCH v3 3/4] apic: Add helper functions apic_match_dest, apic_match_[physical, logical]_dest James Sullivan
2015-04-30 21:49 ` [Qemu-devel] [PATCH v3 4/4] apic: Handle RH=1 and lowpri delivery mode in apic_get_delivery_bitmask() James Sullivan
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