From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58070) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YoF5T-00058u-QE for qemu-devel@nongnu.org; Fri, 01 May 2015 13:50:56 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YoF5S-0002bh-R8 for qemu-devel@nongnu.org; Fri, 01 May 2015 13:50:55 -0400 Received: from mnementh.archaic.org.uk ([2001:8b0:1d0::1]:34037) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YoF5S-0002Wq-Jg for qemu-devel@nongnu.org; Fri, 01 May 2015 13:50:54 -0400 From: Peter Maydell Date: Fri, 1 May 2015 18:50:27 +0100 Message-Id: <1430502643-25909-2-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1430502643-25909-1-git-send-email-peter.maydell@linaro.org> References: <1430502643-25909-1-git-send-email-peter.maydell@linaro.org> Subject: [Qemu-devel] [PATCH v4 01/17] hw/intc/arm_gic: Create outbound FIQ lines List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: "Edgar E. Iglesias" , Greg Bellows , patches@linaro.org From: Fabian Aggeler Create the outbound FIQ lines from the GIC to the CPUs; these are used if the GIC has security extensions or grouping support. Signed-off-by: Fabian Aggeler Signed-off-by: Greg Bellows Message-id: 1429113742-8371-2-git-send-email-greg.bellows@linaro.org [PMM: added FIQ lines to kvm-arm-gic so its interface is the same; tweaked commit message] Signed-off-by: Peter Maydell --- hw/intc/arm_gic.c | 3 +++ hw/intc/arm_gic_kvm.c | 5 ++++- include/hw/intc/arm_gic_common.h | 1 + 3 files changed, 8 insertions(+), 1 deletion(-) diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c index a04c822..e9fb8b9 100644 --- a/hw/intc/arm_gic.c +++ b/hw/intc/arm_gic.c @@ -790,6 +790,9 @@ void gic_init_irqs_and_distributor(GICState *s) for (i = 0; i < NUM_CPU(s); i++) { sysbus_init_irq(sbd, &s->parent_irq[i]); } + for (i = 0; i < NUM_CPU(s); i++) { + sysbus_init_irq(sbd, &s->parent_fiq[i]); + } memory_region_init_io(&s->iomem, OBJECT(s), &gic_dist_ops, s, "gic_dist", 0x1000); } diff --git a/hw/intc/arm_gic_kvm.c b/hw/intc/arm_gic_kvm.c index e1952ad..5aedae1 100644 --- a/hw/intc/arm_gic_kvm.c +++ b/hw/intc/arm_gic_kvm.c @@ -554,12 +554,15 @@ static void kvm_arm_gic_realize(DeviceState *dev, Error **errp) */ i += (GIC_INTERNAL * s->num_cpu); qdev_init_gpio_in(dev, kvm_arm_gic_set_irq, i); - /* We never use our outbound IRQ lines but provide them so that + /* We never use our outbound IRQ/FIQ lines but provide them so that * we maintain the same interface as the non-KVM GIC. */ for (i = 0; i < s->num_cpu; i++) { sysbus_init_irq(sbd, &s->parent_irq[i]); } + for (i = 0; i < s->num_cpu; i++) { + sysbus_init_irq(sbd, &s->parent_fiq[i]); + } /* Try to create the device via the device control API */ s->dev_fd = -1; diff --git a/include/hw/intc/arm_gic_common.h b/include/hw/intc/arm_gic_common.h index f6887ed..01c6f24 100644 --- a/include/hw/intc/arm_gic_common.h +++ b/include/hw/intc/arm_gic_common.h @@ -50,6 +50,7 @@ typedef struct GICState { /*< public >*/ qemu_irq parent_irq[GIC_NCPU]; + qemu_irq parent_fiq[GIC_NCPU]; bool enabled; bool cpu_enabled[GIC_NCPU]; -- 1.9.1