From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58135) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YoF5W-0005D0-EW for qemu-devel@nongnu.org; Fri, 01 May 2015 13:50:59 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YoF5V-0002dT-D0 for qemu-devel@nongnu.org; Fri, 01 May 2015 13:50:58 -0400 Received: from mnementh.archaic.org.uk ([2001:8b0:1d0::1]:34037) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YoF5U-0002Wq-Ox for qemu-devel@nongnu.org; Fri, 01 May 2015 13:50:56 -0400 From: Peter Maydell Date: Fri, 1 May 2015 18:50:31 +0100 Message-Id: <1430502643-25909-6-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1430502643-25909-1-git-send-email-peter.maydell@linaro.org> References: <1430502643-25909-1-git-send-email-peter.maydell@linaro.org> Subject: [Qemu-devel] [PATCH v4 05/17] hw/intc/arm_gic_kvm.c: Save and restore GICD_IGROUPRn state List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: "Edgar E. Iglesias" , Greg Bellows , patches@linaro.org Now that the GIC base class has state fields for the GICD_IGROUPRn registers, make kvm_arm_gic_get() and kvm_arm_gic_put() write and read them. This allows us to remove the check that made us fail migration if the guest had set any of the group register bits. Signed-off-by: Peter Maydell --- hw/intc/arm_gic_kvm.c | 30 ++++++++++++++++++++---------- 1 file changed, 20 insertions(+), 10 deletions(-) diff --git a/hw/intc/arm_gic_kvm.c b/hw/intc/arm_gic_kvm.c index cb47b12..3591ca7 100644 --- a/hw/intc/arm_gic_kvm.c +++ b/hw/intc/arm_gic_kvm.c @@ -176,6 +176,20 @@ static void translate_clear(GICState *s, int irq, int cpu, } } +static void translate_group(GICState *s, int irq, int cpu, + uint32_t *field, bool to_kernel) +{ + int cm = (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU_MASK; + + if (to_kernel) { + *field = GIC_TEST_GROUP(irq, cm); + } else { + if (*field & 1) { + GIC_SET_GROUP(irq, cm); + } + } +} + static void translate_enabled(GICState *s, int irq, int cpu, uint32_t *field, bool to_kernel) { @@ -365,6 +379,9 @@ static void kvm_arm_gic_put(GICState *s) kvm_dist_put(s, 0x180, 1, s->num_irq, translate_clear); kvm_dist_put(s, 0x100, 1, s->num_irq, translate_enabled); + /* irq_state[n].group -> GICD_IGROUPRn */ + kvm_dist_put(s, 0x80, 1, s->num_irq, translate_group); + /* s->irq_target[irq] -> GICD_ITARGETSRn * (restore targets before pending to ensure the pending state is set on * the appropriate CPU interfaces in the kernel) */ @@ -454,21 +471,14 @@ static void kvm_arm_gic_get(GICState *s) /* GICD_IIDR -> ? */ kvm_gicd_access(s, 0x8, 0, ®, false); - /* Verify no GROUP 1 interrupts configured in the kernel */ - for_each_irq_reg(i, s->num_irq, 1) { - kvm_gicd_access(s, 0x80 + (i * 4), 0, ®, false); - if (reg != 0) { - fprintf(stderr, "Unsupported GICD_IGROUPRn value: %08x\n", - reg); - abort(); - } - } - /* Clear all the IRQ settings */ for (i = 0; i < s->num_irq; i++) { memset(&s->irq_state[i], 0, sizeof(s->irq_state[0])); } + /* GICD_IGROUPRn -> irq_state[n].group */ + kvm_dist_get(s, 0x80, 1, s->num_irq, translate_group); + /* GICD_ISENABLERn -> irq_state[n].enabled */ kvm_dist_get(s, 0x100, 1, s->num_irq, translate_enabled); -- 1.9.1