From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35096) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YpX85-0001Rf-0P for qemu-devel@nongnu.org; Tue, 05 May 2015 03:18:58 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YpX84-0003Dm-38 for qemu-devel@nongnu.org; Tue, 05 May 2015 03:18:56 -0400 Received: from mail-wi0-x229.google.com ([2a00:1450:400c:c05::229]:37420) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YpX83-0003DV-QA for qemu-devel@nongnu.org; Tue, 05 May 2015 03:18:56 -0400 Received: by widdi4 with SMTP id di4so134558988wid.0 for ; Tue, 05 May 2015 00:18:55 -0700 (PDT) Sender: Paolo Bonzini From: Paolo Bonzini Date: Tue, 5 May 2015 09:18:24 +0200 Message-Id: <1430810304-7904-4-git-send-email-pbonzini@redhat.com> In-Reply-To: <1430810304-7904-1-git-send-email-pbonzini@redhat.com> References: <1430810304-7904-1-git-send-email-pbonzini@redhat.com> Subject: [Qemu-devel] [PATCH v2 3/3] target-ppc: use separate indices for various translation modes List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: agraf@suse.de, rth@twiddle.net PowerPC TCG flushes the TLB on every IR/DR change, which basically means on every user<->kernel context switch. Encode IR/DR in the MMU index. This brings the number of TLB flushes down from ~900000 to ~50000 for starting up the Debian installer, which is in line with x86 and gives a ~10% performance improvement. Signed-off-by: Paolo Bonzini Message-Id: <1424436345-37924-4-git-send-email-pbonzini@redhat.com> --- target-ppc/cpu.h | 12 +++++++----- target-ppc/excp_helper.c | 3 --- target-ppc/helper_regs.h | 15 +++++++++------ 3 files changed, 16 insertions(+), 14 deletions(-) diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h index c05c503..2c41d49 100644 --- a/target-ppc/cpu.h +++ b/target-ppc/cpu.h @@ -944,7 +944,13 @@ struct ppc_segment_page_sizes { /*****************************************************************************/ /* The whole PowerPC CPU context */ -#define NB_MMU_MODES 3 +#define NB_MMU_MODES 12 +#define MMU_IDX_IR 1 +#define MMU_IDX_DR 2 +#define MMU_IDX_PR 0 +#define MMU_IDX_SUP 4 +#define MMU_IDX_HV 8 +#define MMU_USER_IDX (MMU_IDX_PR|MMU_IDX_IR|MMU_IDX_DR) #define PPC_CPU_OPCODES_LEN 0x40 #define PPC_CPU_INDIRECT_OPCODES_LEN 0x20 @@ -1246,10 +1252,6 @@ int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val); #define cpu_list ppc_cpu_list /* MMU modes definitions */ -#define MMU_MODE0_SUFFIX _user -#define MMU_MODE1_SUFFIX _kernel -#define MMU_MODE2_SUFFIX _hypv -#define MMU_USER_IDX 0 static inline int cpu_mmu_index (CPUPPCState *env) { return env->mmu_idx; diff --git a/target-ppc/excp_helper.c b/target-ppc/excp_helper.c index b803475..f608701 100644 --- a/target-ppc/excp_helper.c +++ b/target-ppc/excp_helper.c @@ -623,9 +623,6 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp) if (env->spr[SPR_LPCR] & LPCR_AIL) { new_msr |= (1 << MSR_IR) | (1 << MSR_DR); - } else if (msr & ((1 << MSR_IR) | (1 << MSR_DR))) { - /* If we disactivated any translation, flush TLBs */ - tlb_flush(cs, 1); } #ifdef TARGET_PPC64 diff --git a/target-ppc/helper_regs.h b/target-ppc/helper_regs.h index 271fddf..5dfc54f 100644 --- a/target-ppc/helper_regs.h +++ b/target-ppc/helper_regs.h @@ -41,12 +41,17 @@ static inline void hreg_swap_gpr_tgpr(CPUPPCState *env) static inline void hreg_compute_mem_idx(CPUPPCState *env) { + int mmu_idx; + /* Precompute MMU index */ - if (msr_pr == 0 && msr_hv != 0) { - env->mmu_idx = 2; + if (msr_pr == 1) { + mmu_idx = MMU_IDX_PR; } else { - env->mmu_idx = 1 - msr_pr; + mmu_idx = msr_hv ? MMU_IDX_HV : MMU_IDX_SUP; } + mmu_idx |= msr_ir ? MMU_IDX_IR : 0; + mmu_idx |= msr_dr ? MMU_IDX_DR : 0; + env->mmu_idx = mmu_idx; } static inline void hreg_compute_hflags(CPUPPCState *env) @@ -56,7 +61,7 @@ static inline void hreg_compute_hflags(CPUPPCState *env) /* We 'forget' FE0 & FE1: we'll never generate imprecise exceptions */ hflags_mask = (1 << MSR_VR) | (1 << MSR_AP) | (1 << MSR_SA) | (1 << MSR_PR) | (1 << MSR_FP) | (1 << MSR_SE) | (1 << MSR_BE) | - (1 << MSR_LE) | (1 << MSR_VSX); + (1 << MSR_LE) | (1 << MSR_VSX) | (1 << MSR_IR) | (1 << MSR_DR); hflags_mask |= (1ULL << MSR_CM) | (1ULL << MSR_SF) | MSR_HVB; hreg_compute_mem_idx(env); env->hflags = env->msr & hflags_mask; @@ -82,8 +87,6 @@ static inline int hreg_store_msr(CPUPPCState *env, target_ulong value, } if (((value >> MSR_IR) & 1) != msr_ir || ((value >> MSR_DR) & 1) != msr_dr) { - /* Flush all tlb when changing translation mode */ - tlb_flush(cs, 1); excp = POWERPC_EXCP_NONE; cs->interrupt_request |= CPU_INTERRUPT_EXITTB; } -- 2.3.5