From: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
To: qemu-devel@nongnu.org
Subject: [Qemu-devel] [PATCH 1/5] target-tricore: Fix LOOP using wrong register for compare
Date: Tue, 5 May 2015 19:46:59 +0200 [thread overview]
Message-ID: <1430848023-21048-2-git-send-email-kbastian@mail.uni-paderborn.de> (raw)
In-Reply-To: <1430848023-21048-1-git-send-email-kbastian@mail.uni-paderborn.de>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
---
target-tricore/translate.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target-tricore/translate.c b/target-tricore/translate.c
index 54a48cd..d2cd640 100644
--- a/target-tricore/translate.c
+++ b/target-tricore/translate.c
@@ -3440,7 +3440,7 @@ static void gen_compute_branch(DisasContext *ctx, uint32_t opc, int r1,
break;
case OPCM_32_BRR_LOOP:
if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_LOOP) {
- gen_loop(ctx, r1, offset * 2);
+ gen_loop(ctx, r2, offset * 2);
} else {
/* OPC2_32_BRR_LOOPU */
gen_goto_tb(ctx, 0, ctx->pc + offset * 2);
--
2.3.7
next prev parent reply other threads:[~2015-05-05 17:47 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-05-05 17:46 [Qemu-devel] [PATCH 0/5] TriCore bugfixes Bastian Koppelmann
2015-05-05 17:46 ` Bastian Koppelmann [this message]
2015-05-05 17:47 ` [Qemu-devel] [PATCH 2/5] target-tricore: fix SLR_LD_W and SLR_LD_W_POSTINC insn being a 2 byte memory access insted of 4 Bastian Koppelmann
2015-05-05 17:47 ` [Qemu-devel] [PATCH 3/5] target-tricore: fix BO_OFF10_SEXT calculating the wrong offset Bastian Koppelmann
2015-05-05 17:47 ` [Qemu-devel] [PATCH 4/5] target-tricore: fix rslcx restoring the upper context instead of the lower Bastian Koppelmann
2015-05-05 17:47 ` [Qemu-devel] [PATCH 5/5] target-tricore: fix rfe not restoring the PC Bastian Koppelmann
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