From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47931) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YpzwU-0004AM-G0 for qemu-devel@nongnu.org; Wed, 06 May 2015 10:04:55 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YpzwT-0002eZ-6d for qemu-devel@nongnu.org; Wed, 06 May 2015 10:04:54 -0400 Received: from mail-wg0-x230.google.com ([2a00:1450:400c:c00::230]:35227) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YpzwS-0002eR-Po for qemu-devel@nongnu.org; Wed, 06 May 2015 10:04:53 -0400 Received: by wgyo15 with SMTP id o15so12875552wgy.2 for ; Wed, 06 May 2015 07:04:52 -0700 (PDT) From: shlomopongratz@gmail.com Date: Wed, 6 May 2015 17:04:41 +0300 Message-Id: <1430921082-16779-4-git-send-email-shlomopongratz@gmail.com> In-Reply-To: <1430921082-16779-1-git-send-email-shlomopongratz@gmail.com> References: <1430921082-16779-1-git-send-email-shlomopongratz@gmail.com> Subject: [Qemu-devel] [PATCH RFC V2 3/4] GICv3 support List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, Shlomo Pongratz From: Shlomo Pongratz Add system instructions used by the Linux (kernel) GICv3 device driver Signed-off-by: Shlomo Pongratz --- target-arm/cpu.h | 8 ++++++ target-arm/cpu64.c | 84 ++++++++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 92 insertions(+) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index d4a5899..de53e9a 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -1008,6 +1008,14 @@ void armv7m_nvic_set_pending(void *opaque, int irq); int armv7m_nvic_acknowledge_irq(void *opaque); void armv7m_nvic_complete_irq(void *opaque, int irq); +void armv8_gicv3_set_sgi(void *opaque, int cpuindex, uint64_t value); +uint64_t armv8_gicv3_acknowledge_irq(void *opaque, int cpuindex); +void armv8_gicv3_complete_irq(void *opaque, int cpuindex, int irq); +uint64_t armv8_gicv3_get_priority_mask(void *opaque, int cpuindex); +void armv8_gicv3_set_priority_mask(void *opaque, int cpuindex, uint32_t mask); +uint64_t armv8_gicv3_get_sre(void *opaque); +void armv8_gicv3_set_sre(void *opaque, uint64_t sre); + /* Interface for defining coprocessor registers. * Registers are defined in tables of arm_cp_reginfo structs * which are passed to define_arm_cp_regs(). diff --git a/target-arm/cpu64.c b/target-arm/cpu64.c index 270bc2f..f3cb13f 100644 --- a/target-arm/cpu64.c +++ b/target-arm/cpu64.c @@ -45,6 +45,54 @@ static uint64_t a57_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri) } #endif +#ifndef CONFIG_USER_ONLY +static void sgi_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) +{ + CPUState *cpu = ENV_GET_CPU(env); + armv8_gicv3_set_sgi(env->nvic, cpu->cpu_index, value); +} + +static uint64_t iar_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + uint64_t value; + CPUState *cpu = ENV_GET_CPU(env); + value = armv8_gicv3_acknowledge_irq(env->nvic, cpu->cpu_index); + return value; +} + +static void sre_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) +{ + armv8_gicv3_set_sre(env->nvic, value); +} + +static uint64_t sre_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + uint64_t value; + value = armv8_gicv3_get_sre(env->nvic); + return value; +} + +static void eoir_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) +{ + CPUState *cpu = ENV_GET_CPU(env); + armv8_gicv3_complete_irq(env->nvic, cpu->cpu_index, value); +} + +static uint64_t pmr_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + uint64_t value; + CPUState *cpu = ENV_GET_CPU(env); + value = armv8_gicv3_get_priority_mask(env->nvic, cpu->cpu_index); + return value; +} + +static void pmr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) +{ + CPUState *cpu = ENV_GET_CPU(env); + armv8_gicv3_set_priority_mask(env->nvic, cpu->cpu_index, value); +} +#endif + static const ARMCPRegInfo cortexa57_cp_reginfo[] = { #ifndef CONFIG_USER_ONLY { .name = "L2CTLR_EL1", .state = ARM_CP_STATE_AA64, @@ -89,6 +137,42 @@ static const ARMCPRegInfo cortexa57_cp_reginfo[] = { { .name = "L2MERRSR", .cp = 15, .opc1 = 3, .crm = 15, .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 }, + { .name = "EIOR1_EL1", .state = ARM_CP_STATE_AA64, +#ifndef CONFIG_USER_ONLY + .writefn = eoir_write, +#endif + .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 12, .opc2 = 1, + .access = PL1_W, .type = ARM_CP_SPECIAL, .resetvalue = 0 }, + { .name = "IAR1_EL1", .state = ARM_CP_STATE_AA64, +#ifndef CONFIG_USER_ONLY + .readfn = iar_read, +#endif + .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 12, .opc2 = 0, + .access = PL1_R, .type = ARM_CP_SPECIAL, .resetvalue = 0 }, + { .name = "SGI1R_EL1", .state = ARM_CP_STATE_AA64, +#ifndef CONFIG_USER_ONLY + .writefn = sgi_write, +#endif + .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 11, .opc2 = 5, + .access = PL1_RW, .type = ARM_CP_SPECIAL, .resetvalue = 0 }, + { .name = "PMR_EL1", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 6, .opc2 = 0, +#ifndef CONFIG_USER_ONLY + .readfn = pmr_read, .writefn = pmr_write, +#endif + .access = PL1_RW, .type = ARM_CP_SPECIAL, .resetvalue = 0 }, + { .name = "CTLR_EL1", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 12, .opc2 = 4, + .access = PL1_RW, .type = ARM_CP_SPECIAL, .resetvalue = 0 }, + { .name = "SRE_EL1", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 12, .opc2 = 5, .resetvalue = 0, +#ifndef CONFIG_USER_ONLY + .readfn = sre_read, .writefn = sre_write, +#endif + .access = PL1_RW, .type = ARM_CP_SPECIAL, .resetvalue = 0 }, + { .name = "IGRPEN1_EL1", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 12, .opc2 = 7, + .access = PL1_RW, .type = ARM_CP_SPECIAL, .resetvalue = 0 }, REGINFO_SENTINEL }; -- 1.9.1