From: Alvise Rigo <a.rigo@virtualopensystems.com>
To: qemu-devel@nongnu.org
Cc: mttcg@listserver.greensocs.com, jani.kokkonen@huawei.com,
tech@virtualopensystems.com, claudio.fontana@huawei.com
Subject: [Qemu-devel] [RFC 1/5] exec: Add new exclusive bitmap to ram_list
Date: Wed, 6 May 2015 17:38:03 +0200 [thread overview]
Message-ID: <1430926687-25875-2-git-send-email-a.rigo@virtualopensystems.com> (raw)
In-Reply-To: <1430926687-25875-1-git-send-email-a.rigo@virtualopensystems.com>
The purpose of this new bitmap is to flag the memory pages that are in
the middle of LL/SC operations (after a LL, before a SC).
For all these pages, the corresponding TLB entries will be generated
in such a way to force the slow-path.
The accessors to this bitmap are currently not atomic, but they have to
be so in a real multi-threading TCG.
Suggested-by: Jani Kokkonen <jani.kokkonen@huawei.com>
Suggested-by: Claudio Fontana <claudio.fontana@huawei.com>
Signed-off-by: Alvise Rigo <a.rigo@virtualopensystems.com>
---
include/exec/cpu-defs.h | 2 ++
include/exec/memory.h | 3 ++-
include/exec/ram_addr.h | 19 ++++++++++++++++++-
3 files changed, 22 insertions(+), 2 deletions(-)
diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h
index 0ca6f0b..d12cb4c 100644
--- a/include/exec/cpu-defs.h
+++ b/include/exec/cpu-defs.h
@@ -123,5 +123,7 @@ QEMU_BUILD_BUG_ON(sizeof(CPUTLBEntry) != (1 << CPU_TLB_ENTRY_BITS));
#define CPU_COMMON \
/* soft mmu support */ \
CPU_COMMON_TLB \
+ /* true if in the middle of a LoadLink/StoreConditional */ \
+ bool ll_sc_context; \
#endif
diff --git a/include/exec/memory.h b/include/exec/memory.h
index 06ffa1d..aadd2cc 100644
--- a/include/exec/memory.h
+++ b/include/exec/memory.h
@@ -19,7 +19,8 @@
#define DIRTY_MEMORY_VGA 0
#define DIRTY_MEMORY_CODE 1
#define DIRTY_MEMORY_MIGRATION 2
-#define DIRTY_MEMORY_NUM 3 /* num of dirty bits */
+#define DIRTY_MEMORY_EXCLUSIVE 3
+#define DIRTY_MEMORY_NUM 4 /* num of dirty bits */
#include <stdint.h>
#include <stdbool.h>
diff --git a/include/exec/ram_addr.h b/include/exec/ram_addr.h
index ff558a4..7a448ea 100644
--- a/include/exec/ram_addr.h
+++ b/include/exec/ram_addr.h
@@ -21,6 +21,7 @@
#ifndef CONFIG_USER_ONLY
#include "hw/xen/xen.h"
+#include "qemu/bitmap.h"
ram_addr_t qemu_ram_alloc_from_file(ram_addr_t size, MemoryRegion *mr,
bool share, const char *mem_path,
@@ -199,9 +200,25 @@ static inline void cpu_physical_memory_clear_dirty_range(ram_addr_t start,
cpu_physical_memory_clear_dirty_range_type(start, length, DIRTY_MEMORY_CODE);
}
-
void cpu_physical_memory_reset_dirty(ram_addr_t start, ram_addr_t length,
unsigned client);
+static inline void cpu_physical_memory_set_excl_dirty(ram_addr_t addr)
+{
+ clear_bit(addr >> TARGET_PAGE_BITS,
+ ram_list.dirty_memory[DIRTY_MEMORY_EXCLUSIVE]);
+}
+
+static inline int cpu_physical_memory_excl_is_dirty(ram_addr_t addr)
+{
+ return !test_bit(addr >> TARGET_PAGE_BITS,
+ ram_list.dirty_memory[DIRTY_MEMORY_EXCLUSIVE]);
+}
+
+static inline void cpu_physical_memory_clear_excl_dirty(ram_addr_t addr)
+{
+ set_bit(addr >> TARGET_PAGE_BITS,
+ ram_list.dirty_memory[DIRTY_MEMORY_EXCLUSIVE]);
+}
#endif
#endif
--
2.4.0
next prev parent reply other threads:[~2015-05-06 15:37 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-05-06 15:38 [Qemu-devel] [RFC 0/5] Slow-path for atomic instruction translation Alvise Rigo
2015-05-06 15:38 ` Alvise Rigo [this message]
2015-05-07 17:12 ` [Qemu-devel] [RFC 1/5] exec: Add new exclusive bitmap to ram_list Richard Henderson
2015-05-11 7:48 ` alvise rigo
2015-05-06 15:38 ` [Qemu-devel] [RFC 2/5] Add new TLB_EXCL flag Alvise Rigo
2015-05-07 17:25 ` Richard Henderson
2015-05-11 7:47 ` alvise rigo
2015-05-06 15:38 ` [Qemu-devel] [RFC 3/5] softmmu: Add helpers for a new slow-path Alvise Rigo
2015-05-07 17:56 ` Richard Henderson
2015-05-11 8:07 ` alvise rigo
2015-05-06 15:38 ` [Qemu-devel] [RFC 4/5] tcg-op: create new TCG qemu_ldlink and qemu_stcond instructions Alvise Rigo
2015-05-07 17:58 ` Richard Henderson
2015-05-11 8:12 ` alvise rigo
2015-05-06 15:38 ` [Qemu-devel] [RFC 5/5] target-arm: translate: implement qemu_ldlink and qemu_stcond ops Alvise Rigo
2015-05-06 15:51 ` [Qemu-devel] [RFC 0/5] Slow-path for atomic instruction translation Paolo Bonzini
2015-05-06 16:00 ` Mark Burton
2015-05-06 16:21 ` alvise rigo
2015-05-06 15:55 ` Mark Burton
2015-05-06 16:19 ` alvise rigo
2015-05-06 16:20 ` Mark Burton
2015-05-08 15:22 ` Alex Bennée
2015-05-11 9:08 ` alvise rigo
2015-05-08 18:29 ` Emilio G. Cota
2015-05-11 9:10 ` alvise rigo
2015-05-26 21:51 ` Emilio G. Cota
2015-05-27 7:20 ` alvise rigo
2015-05-27 8:51 ` Alex Bennée
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