From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44292) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Yq1OV-0004mE-2K for qemu-devel@nongnu.org; Wed, 06 May 2015 11:37:58 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Yq1OR-0003pC-ST for qemu-devel@nongnu.org; Wed, 06 May 2015 11:37:54 -0400 Received: from mail-wi0-f174.google.com ([209.85.212.174]:33405) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Yq1OR-0003o5-K1 for qemu-devel@nongnu.org; Wed, 06 May 2015 11:37:51 -0400 Received: by wief7 with SMTP id f7so128381553wie.0 for ; Wed, 06 May 2015 08:37:51 -0700 (PDT) From: Alvise Rigo Date: Wed, 6 May 2015 17:38:06 +0200 Message-Id: <1430926687-25875-5-git-send-email-a.rigo@virtualopensystems.com> In-Reply-To: <1430926687-25875-1-git-send-email-a.rigo@virtualopensystems.com> References: <1430926687-25875-1-git-send-email-a.rigo@virtualopensystems.com> Subject: [Qemu-devel] [RFC 4/5] tcg-op: create new TCG qemu_ldlink and qemu_stcond instructions List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: mttcg@listserver.greensocs.com, jani.kokkonen@huawei.com, tech@virtualopensystems.com, claudio.fontana@huawei.com Create a new pair of instructions that implement a LoadLink/StoreConditional mechanism. Suggested-by: Jani Kokkonen Suggested-by: Claudio Fontana Signed-off-by: Alvise Rigo --- tcg/tcg-op.c | 20 ++++++++++++++++++++ tcg/tcg-op.h | 3 +++ tcg/tcg-opc.h | 4 ++++ tcg/tcg.c | 2 ++ 4 files changed, 29 insertions(+) diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index 2b6be75..7c3e85b 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -1886,6 +1886,13 @@ static void gen_ldst_i32(TCGOpcode opc, TCGv_i32 val, TCGv addr, #endif } +/* An output operand to return the StoreConditional result */ +static void gen_stcond_i32(TCGOpcode opc, TCGv_i32 is_dirty, TCGv_i32 val, + TCGv addr, TCGMemOp memop, TCGArg idx) +{ + tcg_gen_op5ii_i32(opc, is_dirty, val, addr, memop, idx); +} + static void gen_ldst_i64(TCGOpcode opc, TCGv_i64 val, TCGv addr, TCGMemOp memop, TCGArg idx) { @@ -1913,12 +1920,25 @@ void tcg_gen_qemu_ld_i32(TCGv_i32 val, TCGv addr, TCGArg idx, TCGMemOp memop) gen_ldst_i32(INDEX_op_qemu_ld_i32, val, addr, memop, idx); } +void tcg_gen_qemu_ldlink_i32(TCGv_i32 val, TCGv addr, TCGArg idx, TCGMemOp memop) +{ + memop = tcg_canonicalize_memop(memop, 0, 0); + gen_ldst_i32(INDEX_op_qemu_ldlink_i32, val, addr, memop, idx); +} + void tcg_gen_qemu_st_i32(TCGv_i32 val, TCGv addr, TCGArg idx, TCGMemOp memop) { memop = tcg_canonicalize_memop(memop, 0, 1); gen_ldst_i32(INDEX_op_qemu_st_i32, val, addr, memop, idx); } +void tcg_gen_qemu_stcond_i32(TCGv_i32 is_dirty, TCGv_i32 val, TCGv addr, + TCGArg idx, TCGMemOp memop) +{ + memop = tcg_canonicalize_memop(memop, 0, 1); + gen_stcond_i32(INDEX_op_qemu_stcond_i32, is_dirty, val, addr, memop, idx); +} + void tcg_gen_qemu_ld_i64(TCGv_i64 val, TCGv addr, TCGArg idx, TCGMemOp memop) { if (TCG_TARGET_REG_BITS == 32 && (memop & MO_SIZE) < MO_64) { diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h index d1d763f..f183169 100644 --- a/tcg/tcg-op.h +++ b/tcg/tcg-op.h @@ -754,6 +754,9 @@ void tcg_gen_qemu_st_i32(TCGv_i32, TCGv, TCGArg, TCGMemOp); void tcg_gen_qemu_ld_i64(TCGv_i64, TCGv, TCGArg, TCGMemOp); void tcg_gen_qemu_st_i64(TCGv_i64, TCGv, TCGArg, TCGMemOp); +void tcg_gen_qemu_ldlink_i32(TCGv_i32, TCGv, TCGArg, TCGMemOp); +void tcg_gen_qemu_stcond_i32(TCGv_i32, TCGv_i32, TCGv, TCGArg, TCGMemOp); + static inline void tcg_gen_qemu_ld8u(TCGv ret, TCGv addr, int mem_index) { tcg_gen_qemu_ld_tl(ret, addr, mem_index, MO_UB); diff --git a/tcg/tcg-opc.h b/tcg/tcg-opc.h index 42d0cfe..c88411c 100644 --- a/tcg/tcg-opc.h +++ b/tcg/tcg-opc.h @@ -183,6 +183,10 @@ DEF(qemu_ld_i32, 1, TLADDR_ARGS, 2, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) DEF(qemu_st_i32, 0, TLADDR_ARGS + 1, 2, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) +DEF(qemu_ldlink_i32, 1, TLADDR_ARGS, 2, + TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) +DEF(qemu_stcond_i32, 1, TLADDR_ARGS + 1, 2, + TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) DEF(qemu_ld_i64, DATA64_ARGS, TLADDR_ARGS, 2, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS | TCG_OPF_64BIT) DEF(qemu_st_i64, 0, TLADDR_ARGS + DATA64_ARGS, 2, diff --git a/tcg/tcg.c b/tcg/tcg.c index f1558b7..368f6ae 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -1068,6 +1068,8 @@ void tcg_dump_ops(TCGContext *s) i = 1; break; case INDEX_op_qemu_ld_i32: + case INDEX_op_qemu_ldlink_i32: + case INDEX_op_qemu_stcond_i32: case INDEX_op_qemu_st_i32: case INDEX_op_qemu_ld_i64: case INDEX_op_qemu_st_i64: -- 2.4.0