[Qemu-devel] [PATCH v2 2/6] Introduce RAM location in vendor specific area in TIS

[Stefan Berger <stefanb@linux.vnet.ibm.com>]

Introduce RAM locations in the vendor specific area in the TIS. These
locations will survive a reset and will be part of the state written
during a suspend. Their purpose is to support the physical presence
interface where the OS (ACPI) and the firmware (SeaBIOS) use these RAM
locations to exchange data.

Only locality 0 is used, leaving localities 1-4 available for other extensions.

Signed-off-by: Stefan Berger <stefanb@linux.vnet.ibm.com>
---
 hw/tpm/tpm_tis.c | 27 +++++++++++++++++++++++++++
 hw/tpm/tpm_tis.h |  2 ++
 2 files changed, 29 insertions(+)

diff --git a/hw/tpm/tpm_tis.c b/hw/tpm/tpm_tis.c
index daf2ac9..1fb4e17 100644
--- a/hw/tpm/tpm_tis.c
+++ b/hw/tpm/tpm_tis.c
@@ -61,6 +61,7 @@
 
 /* vendor-specific registers */
 #define TPM_TIS_REG_DEBUG                 0xf90
+#define TPM_TIS_REG_RAM                   0xfa0
 
 #define TPM_TIS_STS_TPM_FAMILY_MASK         (0x3 << 26)/* TPM 2.0 */
 #define TPM_TIS_STS_TPM_FAMILY1_2           (0 << 26)  /* TPM 2.0 */
@@ -503,6 +504,7 @@ static uint64_t tpm_tis_mmio_read(void *opaque, hwaddr addr,
     uint8_t locty = tpm_tis_locality_from_addr(addr);
     uint32_t avail;
     uint8_t v;
+    int c;
 
     if (tpm_backend_had_startup_error(s->be_driver)) {
         return val;
@@ -599,6 +601,18 @@ static uint64_t tpm_tis_mmio_read(void *opaque, hwaddr addr,
         tpm_tis_dump_state(opaque, addr);
         break;
 #endif
+    case TPM_TIS_REG_RAM ... 0xfff:
+        if (locty == 0) {
+            /* RAM only in locality 0 -- allow unaligned accesses */
+            offset = addr & 0xfff;
+            shift = 0;
+
+            for (c = size - 1; c >= 0; c--) {
+                val <<= 8;
+                val |= tis->locty0_ram[offset - TPM_TIS_REG_RAM + c];
+            }
+        }
+        break;
     }
 
     if (shift) {
@@ -938,6 +952,19 @@ static void tpm_tis_mmio_write_intern(void *opaque, hwaddr addr,
             }
         }
         break;
+
+    case TPM_TIS_REG_RAM ... 0xfff:
+        if (locty == 0) {
+            /* RAM only in locality 0 -- allow unaligned accesses */
+            off = addr & 0xfff;
+            val >>= shift;
+            /* only support locality 0 */
+            for (c = 0; c <= size - 1; c++) {
+                tis->locty0_ram[off - TPM_TIS_REG_RAM + c] = val;
+                val >>= 8;
+            }
+        }
+        break;
     }
 }
 
diff --git a/hw/tpm/tpm_tis.h b/hw/tpm/tpm_tis.h
index a1df41f..0e98cb0 100644
--- a/hw/tpm/tpm_tis.h
+++ b/hw/tpm/tpm_tis.h
@@ -65,6 +65,8 @@ typedef struct TPMTISEmuState {
 
     qemu_irq irq;
     uint32_t irq_num;
+
+    uint8_t locty0_ram[0x60]; /* a vendor spec. extension at 0xfa0-0xfff in locality 0 */
 } TPMTISEmuState;
 
 #endif /* TPM_TPM_TIS_H */
-- 
1.9.3