From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49985) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Yqkw5-0003DZ-1b for qemu-devel@nongnu.org; Fri, 08 May 2015 12:15:37 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Yqkw1-0002To-Qk for qemu-devel@nongnu.org; Fri, 08 May 2015 12:15:36 -0400 Received: from e34.co.us.ibm.com ([32.97.110.152]:57151) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Yqkw0-0002TQ-To for qemu-devel@nongnu.org; Fri, 08 May 2015 12:15:33 -0400 Received: from /spool/local by e34.co.us.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted for from ; Fri, 8 May 2015 10:15:32 -0600 Received: from b03cxnp08028.gho.boulder.ibm.com (b03cxnp08028.gho.boulder.ibm.com [9.17.130.20]) by d03dlp03.boulder.ibm.com (Postfix) with ESMTP id 438FF19D803F for ; Fri, 8 May 2015 10:06:33 -0600 (MDT) Received: from d03av03.boulder.ibm.com (d03av03.boulder.ibm.com [9.17.195.169]) by b03cxnp08028.gho.boulder.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id t48GF6B440435792 for ; Fri, 8 May 2015 09:15:06 -0700 Received: from d03av03.boulder.ibm.com (localhost [127.0.0.1]) by d03av03.boulder.ibm.com (8.14.4/8.14.4/NCO v10.0 AVout) with ESMTP id t48GFRsL010482 for ; Fri, 8 May 2015 10:15:28 -0600 From: Stefan Berger Date: Fri, 8 May 2015 12:15:16 -0400 Message-Id: <1431101720-701152-3-git-send-email-stefanb@linux.vnet.ibm.com> In-Reply-To: <1431101720-701152-1-git-send-email-stefanb@linux.vnet.ibm.com> References: <1431101720-701152-1-git-send-email-stefanb@linux.vnet.ibm.com> Subject: [Qemu-devel] [PATCH v2 2/6] Introduce RAM location in vendor specific area in TIS List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org, mst@redhat.com Cc: imammedo@redhat.com, kevin@koconnor.net, stefanb@us.ibm.com, quan.xu@intel.com, Stefan Berger Introduce RAM locations in the vendor specific area in the TIS. These locations will survive a reset and will be part of the state written during a suspend. Their purpose is to support the physical presence interface where the OS (ACPI) and the firmware (SeaBIOS) use these RAM locations to exchange data. Only locality 0 is used, leaving localities 1-4 available for other extensions. Signed-off-by: Stefan Berger --- hw/tpm/tpm_tis.c | 27 +++++++++++++++++++++++++++ hw/tpm/tpm_tis.h | 2 ++ 2 files changed, 29 insertions(+) diff --git a/hw/tpm/tpm_tis.c b/hw/tpm/tpm_tis.c index daf2ac9..1fb4e17 100644 --- a/hw/tpm/tpm_tis.c +++ b/hw/tpm/tpm_tis.c @@ -61,6 +61,7 @@ /* vendor-specific registers */ #define TPM_TIS_REG_DEBUG 0xf90 +#define TPM_TIS_REG_RAM 0xfa0 #define TPM_TIS_STS_TPM_FAMILY_MASK (0x3 << 26)/* TPM 2.0 */ #define TPM_TIS_STS_TPM_FAMILY1_2 (0 << 26) /* TPM 2.0 */ @@ -503,6 +504,7 @@ static uint64_t tpm_tis_mmio_read(void *opaque, hwaddr addr, uint8_t locty = tpm_tis_locality_from_addr(addr); uint32_t avail; uint8_t v; + int c; if (tpm_backend_had_startup_error(s->be_driver)) { return val; @@ -599,6 +601,18 @@ static uint64_t tpm_tis_mmio_read(void *opaque, hwaddr addr, tpm_tis_dump_state(opaque, addr); break; #endif + case TPM_TIS_REG_RAM ... 0xfff: + if (locty == 0) { + /* RAM only in locality 0 -- allow unaligned accesses */ + offset = addr & 0xfff; + shift = 0; + + for (c = size - 1; c >= 0; c--) { + val <<= 8; + val |= tis->locty0_ram[offset - TPM_TIS_REG_RAM + c]; + } + } + break; } if (shift) { @@ -938,6 +952,19 @@ static void tpm_tis_mmio_write_intern(void *opaque, hwaddr addr, } } break; + + case TPM_TIS_REG_RAM ... 0xfff: + if (locty == 0) { + /* RAM only in locality 0 -- allow unaligned accesses */ + off = addr & 0xfff; + val >>= shift; + /* only support locality 0 */ + for (c = 0; c <= size - 1; c++) { + tis->locty0_ram[off - TPM_TIS_REG_RAM + c] = val; + val >>= 8; + } + } + break; } } diff --git a/hw/tpm/tpm_tis.h b/hw/tpm/tpm_tis.h index a1df41f..0e98cb0 100644 --- a/hw/tpm/tpm_tis.h +++ b/hw/tpm/tpm_tis.h @@ -65,6 +65,8 @@ typedef struct TPMTISEmuState { qemu_irq irq; uint32_t irq_num; + + uint8_t locty0_ram[0x60]; /* a vendor spec. extension at 0xfa0-0xfff in locality 0 */ } TPMTISEmuState; #endif /* TPM_TPM_TIS_H */ -- 1.9.3