From: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
To: qemu-devel@nongnu.org
Subject: [Qemu-devel] [PULL 1/5] target-tricore: Fix LOOP using wrong register for compare
Date: Mon, 11 May 2015 14:30:12 +0200 [thread overview]
Message-ID: <1431347416-32365-2-git-send-email-kbastian@mail.uni-paderborn.de> (raw)
In-Reply-To: <1431347416-32365-1-git-send-email-kbastian@mail.uni-paderborn.de>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
---
target-tricore/translate.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target-tricore/translate.c b/target-tricore/translate.c
index 54a48cd..d2cd640 100644
--- a/target-tricore/translate.c
+++ b/target-tricore/translate.c
@@ -3440,7 +3440,7 @@ static void gen_compute_branch(DisasContext *ctx, uint32_t opc, int r1,
break;
case OPCM_32_BRR_LOOP:
if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_LOOP) {
- gen_loop(ctx, r1, offset * 2);
+ gen_loop(ctx, r2, offset * 2);
} else {
/* OPC2_32_BRR_LOOPU */
gen_goto_tb(ctx, 0, ctx->pc + offset * 2);
--
2.4.0
next prev parent reply other threads:[~2015-05-11 12:30 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-05-11 12:30 [Qemu-devel] [PULL 0/5] tricore-patches Bastian Koppelmann
2015-05-11 12:30 ` Bastian Koppelmann [this message]
2015-05-11 12:30 ` [Qemu-devel] [PULL 2/5] target-tricore: fix SLR_LD_W and SLR_LD_W_POSTINC insn being a 2 byte memory access insted of 4 Bastian Koppelmann
2015-05-11 12:30 ` [Qemu-devel] [PULL 3/5] target-tricore: fix BO_OFF10_SEXT calculating the wrong offset Bastian Koppelmann
2015-05-11 12:30 ` [Qemu-devel] [PULL 4/5] target-tricore: fix rslcx restoring the upper context instead of the lower Bastian Koppelmann
2015-05-11 12:30 ` [Qemu-devel] [PULL 5/5] target-tricore: fix rfe not restoring the PC Bastian Koppelmann
2015-05-11 15:07 ` [Qemu-devel] [PULL 0/5] tricore-patches Peter Maydell
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