From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42280) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Yrnwo-0002KX-WB for qemu-devel@nongnu.org; Mon, 11 May 2015 09:40:44 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Yrnwo-0000ak-1b for qemu-devel@nongnu.org; Mon, 11 May 2015 09:40:42 -0400 Received: from mnementh.archaic.org.uk ([2001:8b0:1d0::1]:34139) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Yrnwn-0000ZY-9T for qemu-devel@nongnu.org; Mon, 11 May 2015 09:40:41 -0400 Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.80) (envelope-from ) id 1Yrnwk-0005eZ-Nn for qemu-devel@nongnu.org; Mon, 11 May 2015 14:40:38 +0100 From: Peter Maydell Date: Mon, 11 May 2015 14:40:19 +0100 Message-Id: <1431351638-21705-1-git-send-email-peter.maydell@linaro.org> Subject: [Qemu-devel] [PULL 00/19] target-arm queue List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org This is mostly the GIC TZ changes, with a couple of other minor bugfixes. -- PMM The following changes since commit b951cda21d6b232f138ccf008e12bce8ddc95465: Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into staging (2015-05-11 12:01:09 +0100) are available in the git repository at: git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20150511 for you to fetch changes up to 49855cdaed78f66f501df6e18b8b3b7012cea2eb: hw/arm/highbank.c: Wire FIQ between CPU <> GIC (2015-05-11 14:28:54 +0100) ---------------------------------------------------------------- target-arm queue: * Support TZ and grouping in the GIC * hw/sd: sd_reset cleanup * armv7m_nvic: fix bug in systick device ---------------------------------------------------------------- Adrian Huang (1): armv7m_nvic: systick: Reload the RELOAD value and count down only if ENABLE bit is set Fabian Aggeler (12): hw/intc/arm_gic: Create outbound FIQ lines hw/intc/arm_gic: Add Security Extensions property hw/intc/arm_gic: Add Interrupt Group Registers hw/intc/arm_gic: Make ICDDCR/GICD_CTLR banked hw/intc/arm_gic: Make ICCBPR/GICC_BPR banked hw/intc/arm_gic: Make ICCICR/GICC_CTLR banked hw/intc/arm_gic: Implement Non-secure view of RPR hw/intc/arm_gic: Restrict priority view hw/intc/arm_gic: Handle grouping for GICC_HPPIR hw/intc/arm_gic: Change behavior of EOIR writes hw/intc/arm_gic: Change behavior of IAR writes hw/arm/vexpress.c: Wire FIQ between CPU <> GIC Greg Bellows (1): hw/arm/virt.c: Wire FIQ between CPU <> GIC Peter Maydell (5): hw/sd: Don't pass BlockBackend to sd_reset() hw/intc/arm_gic: Switch to read/write callbacks with tx attributes hw/intc/arm_gic_kvm.c: Save and restore GICD_IGROUPRn state hw/intc/arm_gic: Add grouping support to gic_update() hw/arm/highbank.c: Wire FIQ between CPU <> GIC hw/arm/highbank.c | 3 + hw/arm/vexpress.c | 2 + hw/arm/virt.c | 2 + hw/intc/arm_gic.c | 469 ++++++++++++++++++++++++++++++++------- hw/intc/arm_gic_common.c | 22 +- hw/intc/arm_gic_kvm.c | 51 +++-- hw/intc/armv7m_nvic.c | 17 +- hw/intc/gic_internal.h | 29 ++- hw/sd/sd.c | 17 +- include/hw/intc/arm_gic_common.h | 24 +- 10 files changed, 509 insertions(+), 127 deletions(-)