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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [Qemu-devel] [PULL 11/19] hw/intc/arm_gic: Implement Non-secure view of RPR
Date: Mon, 11 May 2015 14:40:30 +0100	[thread overview]
Message-ID: <1431351638-21705-12-git-send-email-peter.maydell@linaro.org> (raw)
In-Reply-To: <1431351638-21705-1-git-send-email-peter.maydell@linaro.org>

From: Fabian Aggeler <aggelerf@ethz.ch>

For GICs with Security Extensions Non-secure reads have a restricted
view on the current running priority.

Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch>
Signed-off-by: Greg Bellows <greg.bellows@linaro.org>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 1430502643-25909-10-git-send-email-peter.maydell@linaro.org
Message-id: 1429113742-8371-11-git-send-email-greg.bellows@linaro.org
[PMM: make function static, minor comment tweak]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/intc/arm_gic.c | 19 ++++++++++++++++++-
 1 file changed, 18 insertions(+), 1 deletion(-)

diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c
index 4aaaac2..e3bbe9e 100644
--- a/hw/intc/arm_gic.c
+++ b/hw/intc/arm_gic.c
@@ -286,6 +286,23 @@ static void gic_set_cpu_control(GICState *s, int cpu, uint32_t value,
             (s->cpu_ctlr[cpu] & GICC_CTLR_EN_GRP1) ? "En" : "Dis");
 }
 
+static uint8_t gic_get_running_priority(GICState *s, int cpu, MemTxAttrs attrs)
+{
+    if (s->security_extn && !attrs.secure) {
+        if (s->running_priority[cpu] & 0x80) {
+            /* Running priority in upper half of range: return the Non-secure
+             * view of the priority.
+             */
+            return s->running_priority[cpu] << 1;
+        } else {
+            /* Running priority in lower half of range: RAZ */
+            return 0;
+        }
+    } else {
+        return s->running_priority[cpu];
+    }
+}
+
 void gic_complete_irq(GICState *s, int cpu, int irq)
 {
     int update = 0;
@@ -817,7 +834,7 @@ static MemTxResult gic_cpu_read(GICState *s, int cpu, int offset,
         *data = gic_acknowledge_irq(s, cpu);
         break;
     case 0x14: /* Running Priority */
-        *data = s->running_priority[cpu];
+        *data = gic_get_running_priority(s, cpu, attrs);
         break;
     case 0x18: /* Highest Pending Interrupt */
         *data = s->current_pending[cpu];
-- 
1.9.1

  parent reply	other threads:[~2015-05-11 13:40 UTC|newest]

Thread overview: 23+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-05-11 13:40 [Qemu-devel] [PULL 00/19] target-arm queue Peter Maydell
2015-05-11 13:40 ` [Qemu-devel] [PULL 01/19] armv7m_nvic: systick: Reload the RELOAD value and count down only if ENABLE bit is set Peter Maydell
2015-05-11 13:40 ` [Qemu-devel] [PULL 02/19] hw/sd: Don't pass BlockBackend to sd_reset() Peter Maydell
2015-05-11 13:40 ` [Qemu-devel] [PULL 03/19] hw/intc/arm_gic: Create outbound FIQ lines Peter Maydell
2015-05-11 13:40 ` [Qemu-devel] [PULL 04/19] hw/intc/arm_gic: Add Security Extensions property Peter Maydell
2015-05-11 13:40 ` [Qemu-devel] [PULL 05/19] hw/intc/arm_gic: Switch to read/write callbacks with tx attributes Peter Maydell
2015-05-11 13:40 ` [Qemu-devel] [PULL 06/19] hw/intc/arm_gic: Add Interrupt Group Registers Peter Maydell
2015-05-11 13:40 ` [Qemu-devel] [PULL 07/19] hw/intc/arm_gic_kvm.c: Save and restore GICD_IGROUPRn state Peter Maydell
2015-05-11 13:40 ` [Qemu-devel] [PULL 08/19] hw/intc/arm_gic: Make ICDDCR/GICD_CTLR banked Peter Maydell
2015-05-11 13:40 ` [Qemu-devel] [PULL 09/19] hw/intc/arm_gic: Make ICCBPR/GICC_BPR banked Peter Maydell
2015-05-11 13:40 ` [Qemu-devel] [PULL 10/19] hw/intc/arm_gic: Make ICCICR/GICC_CTLR banked Peter Maydell
2015-05-11 13:40 ` Peter Maydell [this message]
2015-05-11 13:40 ` [Qemu-devel] [PULL 12/19] hw/intc/arm_gic: Restrict priority view Peter Maydell
2015-05-11 13:40 ` [Qemu-devel] [PULL 13/19] hw/intc/arm_gic: Handle grouping for GICC_HPPIR Peter Maydell
2015-05-11 13:40 ` [Qemu-devel] [PULL 14/19] hw/intc/arm_gic: Change behavior of EOIR writes Peter Maydell
2015-05-11 13:40 ` [Qemu-devel] [PULL 15/19] hw/intc/arm_gic: Change behavior of IAR writes Peter Maydell
2015-05-11 13:40 ` [Qemu-devel] [PULL 16/19] hw/intc/arm_gic: Add grouping support to gic_update() Peter Maydell
2015-05-11 13:40 ` [Qemu-devel] [PULL 17/19] hw/arm/virt.c: Wire FIQ between CPU <> GIC Peter Maydell
2015-05-11 13:40 ` [Qemu-devel] [PULL 18/19] hw/arm/vexpress.c: " Peter Maydell
2015-05-11 13:40 ` [Qemu-devel] [PULL 19/19] hw/arm/highbank.c: " Peter Maydell
2015-05-12  8:01 ` [Qemu-devel] [PULL 00/19] target-arm queue Peter Maydell
2015-05-12  8:10   ` Peter Crosthwaite
2015-05-12  8:22     ` Peter Maydell

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