From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:45470) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Yro63-0002tC-RF for qemu-devel@nongnu.org; Mon, 11 May 2015 09:50:16 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Yro62-0007G0-VT for qemu-devel@nongnu.org; Mon, 11 May 2015 09:50:15 -0400 Received: from mail-wi0-x22b.google.com ([2a00:1450:400c:c05::22b]:37314) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Yro62-0007Fd-Pb for qemu-devel@nongnu.org; Mon, 11 May 2015 09:50:14 -0400 Received: by widdi4 with SMTP id di4so97201258wid.0 for ; Mon, 11 May 2015 06:50:14 -0700 (PDT) Sender: Paolo Bonzini From: Paolo Bonzini Date: Mon, 11 May 2015 15:49:04 +0200 Message-Id: <1431352157-40283-19-git-send-email-pbonzini@redhat.com> In-Reply-To: <1431352157-40283-1-git-send-email-pbonzini@redhat.com> References: <1431352157-40283-1-git-send-email-pbonzini@redhat.com> Subject: [Qemu-devel] [PATCH 18/31] q35: fix ESMRAMC default List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: lersek@redhat.com, kraxel@redhat.com, mst@redhat.com From: Gerd Hoffmann Signed-off-by: Gerd Hoffmann Signed-off-by: Paolo Bonzini --- hw/pci-host/q35.c | 1 + include/hw/pci-host/q35.h | 7 ++++++- 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/hw/pci-host/q35.c b/hw/pci-host/q35.c index 35b89da..8471d7a 100644 --- a/hw/pci-host/q35.c +++ b/hw/pci-host/q35.c @@ -351,6 +351,7 @@ static void mch_reset(DeviceState *qdev) MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT); d->config[MCH_HOST_BRIDGE_SMRAM] = MCH_HOST_BRIDGE_SMRAM_DEFAULT; + d->config[MCH_HOST_BRIDGE_ESMRAMC] = MCH_HOST_BRIDGE_ESMRAMC_DEFAULT; mch_update(mch); } diff --git a/include/hw/pci-host/q35.h b/include/hw/pci-host/q35.h index 0fff6a2..d3c7bbb 100644 --- a/include/hw/pci-host/q35.h +++ b/include/hw/pci-host/q35.h @@ -128,7 +128,6 @@ typedef struct Q35PCIHost { #define MCH_HOST_BRIDGE_SMRAM 0x9d #define MCH_HOST_BRIDGE_SMRAM_SIZE 2 -#define MCH_HOST_BRIDGE_SMRAM_DEFAULT ((uint8_t)0x2) #define MCH_HOST_BRIDGE_SMRAM_D_OPEN ((uint8_t)(1 << 6)) #define MCH_HOST_BRIDGE_SMRAM_D_CLS ((uint8_t)(1 << 5)) #define MCH_HOST_BRIDGE_SMRAM_D_LCK ((uint8_t)(1 << 4)) @@ -139,6 +138,8 @@ typedef struct Q35PCIHost { #define MCH_HOST_BRIDGE_SMRAM_C_END 0xc0000 #define MCH_HOST_BRIDGE_SMRAM_C_SIZE 0x20000 #define MCH_HOST_BRIDGE_UPPER_SYSTEM_BIOS_END 0x100000 +#define MCH_HOST_BRIDGE_SMRAM_DEFAULT \ + MCH_HOST_BRIDGE_SMRAM_C_BASE_SEG #define MCH_HOST_BRIDGE_ESMRAMC 0x9e #define MCH_HOST_BRIDGE_ESMRAMC_H_SMRAME ((uint8_t)(1 << 7)) @@ -151,6 +152,10 @@ typedef struct Q35PCIHost { #define MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_2MB ((uint8_t)(0x1 << 1)) #define MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_8MB ((uint8_t)(0x2 << 1)) #define MCH_HOST_BRIDGE_ESMRAMC_T_EN ((uint8_t)1) +#define MCH_HOST_BRIDGE_ESMRAMC_DEFAULT \ + (MCH_HOST_BRIDGE_ESMRAMC_SM_CACHE | \ + MCH_HOST_BRIDGE_ESMRAMC_SM_L1 | \ + MCH_HOST_BRIDGE_ESMRAMC_SM_L2) /* D1:F0 PCIE* port*/ #define MCH_PCIE_DEV 1 -- 1.8.3.1