From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:45493) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Yro66-0002wr-3p for qemu-devel@nongnu.org; Mon, 11 May 2015 09:50:18 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Yro65-0007J6-8G for qemu-devel@nongnu.org; Mon, 11 May 2015 09:50:18 -0400 Received: from mail-wi0-x236.google.com ([2a00:1450:400c:c05::236]:34494) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Yro64-0007IY-W6 for qemu-devel@nongnu.org; Mon, 11 May 2015 09:50:17 -0400 Received: by wicmc15 with SMTP id mc15so28702407wic.1 for ; Mon, 11 May 2015 06:50:16 -0700 (PDT) Sender: Paolo Bonzini From: Paolo Bonzini Date: Mon, 11 May 2015 15:49:05 +0200 Message-Id: <1431352157-40283-20-git-send-email-pbonzini@redhat.com> In-Reply-To: <1431352157-40283-1-git-send-email-pbonzini@redhat.com> References: <1431352157-40283-1-git-send-email-pbonzini@redhat.com> Subject: [Qemu-devel] [PATCH 19/31] q35: add config space wmask for SMRAM and ESMRAMC List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: lersek@redhat.com, kraxel@redhat.com, mst@redhat.com From: Gerd Hoffmann Signed-off-by: Gerd Hoffmann Signed-off-by: Paolo Bonzini --- hw/pci-host/q35.c | 2 ++ include/hw/pci-host/q35.h | 9 +++++++++ 2 files changed, 11 insertions(+) diff --git a/hw/pci-host/q35.c b/hw/pci-host/q35.c index 8471d7a..df0032e 100644 --- a/hw/pci-host/q35.c +++ b/hw/pci-host/q35.c @@ -352,6 +352,8 @@ static void mch_reset(DeviceState *qdev) d->config[MCH_HOST_BRIDGE_SMRAM] = MCH_HOST_BRIDGE_SMRAM_DEFAULT; d->config[MCH_HOST_BRIDGE_ESMRAMC] = MCH_HOST_BRIDGE_ESMRAMC_DEFAULT; + d->wmask[MCH_HOST_BRIDGE_SMRAM] = MCH_HOST_BRIDGE_SMRAM_WMASK; + d->wmask[MCH_HOST_BRIDGE_ESMRAMC] = MCH_HOST_BRIDGE_ESMRAMC_WMASK; mch_update(mch); } diff --git a/include/hw/pci-host/q35.h b/include/hw/pci-host/q35.h index d3c7bbb..01b8492 100644 --- a/include/hw/pci-host/q35.h +++ b/include/hw/pci-host/q35.h @@ -140,6 +140,11 @@ typedef struct Q35PCIHost { #define MCH_HOST_BRIDGE_UPPER_SYSTEM_BIOS_END 0x100000 #define MCH_HOST_BRIDGE_SMRAM_DEFAULT \ MCH_HOST_BRIDGE_SMRAM_C_BASE_SEG +#define MCH_HOST_BRIDGE_SMRAM_WMASK \ + (MCH_HOST_BRIDGE_SMRAM_D_OPEN | \ + MCH_HOST_BRIDGE_SMRAM_D_CLS | \ + MCH_HOST_BRIDGE_SMRAM_D_LCK | \ + MCH_HOST_BRIDGE_SMRAM_G_SMRAME) #define MCH_HOST_BRIDGE_ESMRAMC 0x9e #define MCH_HOST_BRIDGE_ESMRAMC_H_SMRAME ((uint8_t)(1 << 7)) @@ -156,6 +161,10 @@ typedef struct Q35PCIHost { (MCH_HOST_BRIDGE_ESMRAMC_SM_CACHE | \ MCH_HOST_BRIDGE_ESMRAMC_SM_L1 | \ MCH_HOST_BRIDGE_ESMRAMC_SM_L2) +#define MCH_HOST_BRIDGE_ESMRAMC_WMASK \ + (MCH_HOST_BRIDGE_ESMRAMC_H_SMRAME | \ + MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_MASK | \ + MCH_HOST_BRIDGE_ESMRAMC_T_EN) /* D1:F0 PCIE* port*/ #define MCH_PCIE_DEV 1 -- 1.8.3.1