From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:45101) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Yro5X-0001pL-8u for qemu-devel@nongnu.org; Mon, 11 May 2015 09:49:44 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Yro5W-0006lw-4v for qemu-devel@nongnu.org; Mon, 11 May 2015 09:49:43 -0400 Received: from mail-wi0-x232.google.com ([2a00:1450:400c:c05::232]:38587) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Yro5V-0006lg-Tq for qemu-devel@nongnu.org; Mon, 11 May 2015 09:49:42 -0400 Received: by wiun10 with SMTP id n10so97142569wiu.1 for ; Mon, 11 May 2015 06:49:41 -0700 (PDT) Sender: Paolo Bonzini From: Paolo Bonzini Date: Mon, 11 May 2015 15:48:48 +0200 Message-Id: <1431352157-40283-3-git-send-email-pbonzini@redhat.com> In-Reply-To: <1431352157-40283-1-git-send-email-pbonzini@redhat.com> References: <1431352157-40283-1-git-send-email-pbonzini@redhat.com> Subject: [Qemu-devel] [PATCH 02/31] target-i386: introduce cpu_get_mem_attrs List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: lersek@redhat.com, kraxel@redhat.com, mst@redhat.com Signed-off-by: Paolo Bonzini --- include/exec/memattrs.h | 4 +++- target-i386/cpu.h | 5 +++++ target-i386/helper.c | 3 ++- target-i386/kvm.c | 2 +- 4 files changed, 11 insertions(+), 3 deletions(-) diff --git a/include/exec/memattrs.h b/include/exec/memattrs.h index 1389b4b..6bbf9aa 100644 --- a/include/exec/memattrs.h +++ b/include/exec/memattrs.h @@ -29,7 +29,9 @@ typedef struct MemTxAttrs { * "didn't specify" if necessary. */ unsigned int unspecified:1; - /* ARM/AMBA TrustZone Secure access */ + /* ARM/AMBA: TrustZone Secure access + * x86: System Management Mode access + */ unsigned int secure:1; /* Memory access is usermode (unprivileged) */ unsigned int user:1; diff --git a/target-i386/cpu.h b/target-i386/cpu.h index 4ee12ca..64c2783 100644 --- a/target-i386/cpu.h +++ b/target-i386/cpu.h @@ -1292,6 +1292,11 @@ static inline void cpu_load_efer(CPUX86State *env, uint64_t val) } } +static inline MemTxAttrs cpu_get_mem_attrs(CPUX86State *env) +{ + return ((MemTxAttrs) { .secure = (env->hflags & HF_SMM_MASK) != 0 }); +} + /* fpu_helper.c */ void cpu_set_mxcsr(CPUX86State *env, uint32_t val); void cpu_set_fpuc(CPUX86State *env, uint16_t val); diff --git a/target-i386/helper.c b/target-i386/helper.c index 4f1ddf7..62e801b 100644 --- a/target-i386/helper.c +++ b/target-i386/helper.c @@ -771,7 +771,8 @@ do_check_protect_pse36: page_offset = vaddr & (page_size - 1); paddr = pte + page_offset; - tlb_set_page(cs, vaddr, paddr, prot, mmu_idx, page_size); + tlb_set_page_with_attrs(cs, vaddr, paddr, cpu_get_mem_attrs(env), + prot, mmu_idx, page_size); return 0; do_fault_rsvd: error_code |= PG_ERROR_RSVD_MASK; diff --git a/target-i386/kvm.c b/target-i386/kvm.c index a26d25a..009bf74 100644 --- a/target-i386/kvm.c +++ b/target-i386/kvm.c @@ -2259,7 +2259,7 @@ MemTxAttrs kvm_arch_post_run(CPUState *cpu, struct kvm_run *run) } cpu_set_apic_tpr(x86_cpu->apic_state, run->cr8); cpu_set_apic_base(x86_cpu->apic_state, run->apic_base); - return MEMTXATTRS_UNSPECIFIED; + return cpu_get_mem_attrs(env); } int kvm_arch_process_async_events(CPUState *cs) -- 1.8.3.1