From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:45169) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Yro5g-000292-GA for qemu-devel@nongnu.org; Mon, 11 May 2015 09:49:53 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Yro5f-0006qL-GJ for qemu-devel@nongnu.org; Mon, 11 May 2015 09:49:52 -0400 Received: from mail-wi0-x233.google.com ([2a00:1450:400c:c05::233]:34451) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Yro5f-0006q0-Ae for qemu-devel@nongnu.org; Mon, 11 May 2015 09:49:51 -0400 Received: by wicmc15 with SMTP id mc15so28692249wic.1 for ; Mon, 11 May 2015 06:49:50 -0700 (PDT) Sender: Paolo Bonzini From: Paolo Bonzini Date: Mon, 11 May 2015 15:48:52 +0200 Message-Id: <1431352157-40283-7-git-send-email-pbonzini@redhat.com> In-Reply-To: <1431352157-40283-1-git-send-email-pbonzini@redhat.com> References: <1431352157-40283-1-git-send-email-pbonzini@redhat.com> Subject: [Qemu-devel] [PATCH 06/31] target-i386: set G=1 in SMM big real mode selectors List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: lersek@redhat.com, kraxel@redhat.com, mst@redhat.com Because the limit field's bits 31:20 is 1, G should be 1. VMX actually enforces this, let's do it for completeness in QEMU as well. Signed-off-by: Paolo Bonzini --- target-i386/smm_helper.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/target-i386/smm_helper.c b/target-i386/smm_helper.c index 6207c3a..5617a14 100644 --- a/target-i386/smm_helper.c +++ b/target-i386/smm_helper.c @@ -177,22 +177,22 @@ void do_smm_enter(X86CPU *cpu) cpu_x86_load_seg_cache(env, R_CS, (env->smbase >> 4) & 0xffff, env->smbase, 0xffffffff, DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | - DESC_A_MASK); + DESC_G_MASK | DESC_A_MASK); cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffffffff, DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | - DESC_A_MASK); + DESC_G_MASK | DESC_A_MASK); cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffffffff, DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | - DESC_A_MASK); + DESC_G_MASK | DESC_A_MASK); cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffffffff, DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | - DESC_A_MASK); + DESC_G_MASK | DESC_A_MASK); cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffffffff, DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | - DESC_A_MASK); + DESC_G_MASK | DESC_A_MASK); cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffffffff, DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | - DESC_A_MASK); + DESC_G_MASK | DESC_A_MASK); } void helper_rsm(CPUX86State *env) -- 1.8.3.1