From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40813) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Ys82z-0007cf-JP for qemu-devel@nongnu.org; Tue, 12 May 2015 07:08:30 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Ys7yh-0007Ym-34 for qemu-devel@nongnu.org; Tue, 12 May 2015 07:04:03 -0400 Received: from mnementh.archaic.org.uk ([2001:8b0:1d0::1]:34148) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Ys7yg-0007Xf-Rh for qemu-devel@nongnu.org; Tue, 12 May 2015 07:03:59 -0400 Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.80) (envelope-from ) id 1Ys7yZ-0007GA-B7 for qemu-devel@nongnu.org; Tue, 12 May 2015 12:03:51 +0100 From: Peter Maydell Date: Tue, 12 May 2015 12:03:51 +0100 Message-Id: <1431428631-27880-1-git-send-email-peter.maydell@linaro.org> Subject: [Qemu-devel] [PULL 00/19] target-arm queue List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org v2 of the pull, fixing a silly compile failure on ARM hosts. Diff is: --- a/hw/intc/arm_gic_kvm.c +++ b/hw/intc/arm_gic_kvm.c @@ -353,8 +353,8 @@ static void kvm_arm_gic_put(GICState *s) * Distributor State */ - /* s->ctlr -> GICD_CTLR */ - reg = s->ctlr; + /* s->enabled -> GICD_CTLR */ + reg = s->enabled; kvm_gicd_access(s, 0x0, 0, ®, true); /* Sanity checking on GICD_TYPER and s->num_irq, s->num_cpu */ @@ -453,9 +453,9 @@ static void kvm_arm_gic_get(GICState *s) * Distributor State */ - /* GICD_CTLR -> s->ctlr */ + /* GICD_CTLR -> s->enabled */ kvm_gicd_access(s, 0x0, 0, ®, false); - s->ctlr = reg; + s->enabled = reg & 1; /* Sanity checking on GICD_TYPER -> s->num_irq, s->num_cpu */ kvm_gicd_access(s, 0x4, 0, ®, false); so I'm not going to resend all the patches, just this cover letter. -- PMM The following changes since commit 19fbe5084c1da6af95177c86e4cab64241d479a8: Merge remote-tracking branch 'remotes/stefanha/tags/net-pull-request' into staging (2015-05-12 10:40:31 +0100) are available in the git repository at: git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20150512 for you to fetch changes up to 5ae79fe825bedc89db8b6bde9d0ed0bb5d59558c: hw/arm/highbank.c: Wire FIQ between CPU <> GIC (2015-05-12 11:57:19 +0100) ---------------------------------------------------------------- target-arm queue: * Support TZ and grouping in the GIC * hw/sd: sd_reset cleanup * armv7m_nvic: fix bug in systick device ---------------------------------------------------------------- Adrian Huang (1): armv7m_nvic: systick: Reload the RELOAD value and count down only if ENABLE bit is set Fabian Aggeler (12): hw/intc/arm_gic: Create outbound FIQ lines hw/intc/arm_gic: Add Security Extensions property hw/intc/arm_gic: Add Interrupt Group Registers hw/intc/arm_gic: Make ICDDCR/GICD_CTLR banked hw/intc/arm_gic: Make ICCBPR/GICC_BPR banked hw/intc/arm_gic: Make ICCICR/GICC_CTLR banked hw/intc/arm_gic: Implement Non-secure view of RPR hw/intc/arm_gic: Restrict priority view hw/intc/arm_gic: Handle grouping for GICC_HPPIR hw/intc/arm_gic: Change behavior of EOIR writes hw/intc/arm_gic: Change behavior of IAR writes hw/arm/vexpress.c: Wire FIQ between CPU <> GIC Greg Bellows (1): hw/arm/virt.c: Wire FIQ between CPU <> GIC Peter Maydell (5): hw/sd: Don't pass BlockBackend to sd_reset() hw/intc/arm_gic: Switch to read/write callbacks with tx attributes hw/intc/arm_gic_kvm.c: Save and restore GICD_IGROUPRn state hw/intc/arm_gic: Add grouping support to gic_update() hw/arm/highbank.c: Wire FIQ between CPU <> GIC hw/arm/highbank.c | 3 + hw/arm/vexpress.c | 2 + hw/arm/virt.c | 2 + hw/intc/arm_gic.c | 469 ++++++++++++++++++++++++++++++++------- hw/intc/arm_gic_common.c | 22 +- hw/intc/arm_gic_kvm.c | 59 +++-- hw/intc/armv7m_nvic.c | 17 +- hw/intc/gic_internal.h | 29 ++- hw/sd/sd.c | 17 +- include/hw/intc/arm_gic_common.h | 24 +- 10 files changed, 513 insertions(+), 131 deletions(-)