From: Richard Henderson <rth@twiddle.net>
To: qemu-devel@nongnu.org
Subject: [Qemu-devel] [PATCH v2 14/17] target-alpha: Raise EXC_M_INV properly for fp inputs
Date: Tue, 12 May 2015 10:39:44 -0700 [thread overview]
Message-ID: <1431452387-20280-15-git-send-email-rth@twiddle.net> (raw)
In-Reply-To: <1431452387-20280-1-git-send-email-rth@twiddle.net>
Ignore DNZ if software completion isn't used. Raise INV for
denormals in system mode so the OS completion handler sees them.
Reported-by: Al Viro <viro@ZenIV.linux.org.uk>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-alpha/fpu_helper.c | 32 ++++++++++++++++++++++----------
target-alpha/helper.h | 1 +
target-alpha/translate.c | 7 +++++++
3 files changed, 30 insertions(+), 10 deletions(-)
diff --git a/target-alpha/fpu_helper.c b/target-alpha/fpu_helper.c
index db523fb..ea1f2e2 100644
--- a/target-alpha/fpu_helper.c
+++ b/target-alpha/fpu_helper.c
@@ -104,16 +104,14 @@ void helper_ieee_input(CPUAlphaState *env, uint64_t val)
uint64_t frac = val & 0xfffffffffffffull;
if (exp == 0) {
- /* Denormals without DNZ set raise an exception. */
- if (frac != 0 && !env->fp_status.flush_inputs_to_zero) {
- arith_excp(env, GETPC(), EXC_M_UNF, 0);
+ /* Denormals without /S raise an exception. */
+ if (frac != 0) {
+ arith_excp(env, GETPC(), EXC_M_INV, 0);
}
} else if (exp == 0x7ff) {
/* Infinity or NaN. */
- /* ??? I'm not sure these exception bit flags are correct. I do
- know that the Linux kernel, at least, doesn't rely on them and
- just emulates the insn to figure out what exception to use. */
- arith_excp(env, GETPC(), frac ? EXC_M_INV : EXC_M_FOV, 0);
+ env->fpcr |= FPCR_INV;
+ arith_excp(env, GETPC(), EXC_M_INV, 0);
}
}
@@ -124,16 +122,30 @@ void helper_ieee_input_cmp(CPUAlphaState *env, uint64_t val)
uint64_t frac = val & 0xfffffffffffffull;
if (exp == 0) {
- /* Denormals without DNZ set raise an exception. */
- if (frac != 0 && !env->fp_status.flush_inputs_to_zero) {
- arith_excp(env, GETPC(), EXC_M_UNF, 0);
+ /* Denormals without /S raise an exception. */
+ if (frac != 0) {
+ arith_excp(env, GETPC(), EXC_M_INV, 0);
}
} else if (exp == 0x7ff && frac) {
/* NaN. */
+ env->fpcr |= FPCR_INV;
arith_excp(env, GETPC(), EXC_M_INV, 0);
}
}
+/* Input handing with software completion. Trap for denorms, unless DNZ
+ is set. If we try to support DNOD (which none of the produced hardware
+ did, AFAICS), we'll need to suppress the trap when FPCR.DNOD is set;
+ then the code downstream of that will need to cope with denorms sans
+ flush_input_to_zero. Most of it should work sanely, but there's
+ nothing to compare with. */
+void helper_ieee_input_s(CPUAlphaState *env, uint64_t val)
+{
+ if (unlikely(2 * val - 1 < 0x1fffffffffffffull)
+ && !env->fp_status.flush_inputs_to_zero) {
+ arith_excp(env, GETPC(), EXC_M_INV | EXC_M_SWC, 0);
+ }
+}
/* S floating (single) */
diff --git a/target-alpha/helper.h b/target-alpha/helper.h
index 5b1a5d9..780b0dc 100644
--- a/target-alpha/helper.h
+++ b/target-alpha/helper.h
@@ -86,6 +86,7 @@ DEF_HELPER_FLAGS_3(fp_exc_raise_s, TCG_CALL_NO_WG, void, env, i32, i32)
DEF_HELPER_FLAGS_2(ieee_input, TCG_CALL_NO_WG, void, env, i64)
DEF_HELPER_FLAGS_2(ieee_input_cmp, TCG_CALL_NO_WG, void, env, i64)
+DEF_HELPER_FLAGS_2(ieee_input_s, TCG_CALL_NO_WG, void, env, i64)
DEF_HELPER_FLAGS_2(cvtql_v_input, TCG_CALL_NO_WG, void, env, i64)
#if !defined (CONFIG_USER_ONLY)
diff --git a/target-alpha/translate.c b/target-alpha/translate.c
index f0556b0..4c441a9 100644
--- a/target-alpha/translate.c
+++ b/target-alpha/translate.c
@@ -658,6 +658,13 @@ static TCGv gen_ieee_input(DisasContext *ctx, int reg, int fn11, int is_cmp)
} else {
gen_helper_ieee_input(cpu_env, val);
}
+ } else {
+#ifndef CONFIG_USER_ONLY
+ /* In system mode, raise exceptions for denormals like real
+ hardware. In user mode, proceed as if the OS completion
+ handler is handling the denormal as per spec. */
+ gen_helper_ieee_input_s(cpu_env, val);
+#endif
}
}
return val;
--
2.1.0
next prev parent reply other threads:[~2015-05-12 17:40 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-05-12 17:39 [Qemu-devel] [PATCH v2 00/17] target-alpha fpu improvments Richard Henderson
2015-05-12 17:39 ` [Qemu-devel] [PATCH v2 01/17] target-alpha: Move VAX helpers to a new file Richard Henderson
2015-05-12 17:39 ` [Qemu-devel] [PATCH v2 02/17] target-alpha: Rename floating-point subroutines Richard Henderson
2015-05-12 17:39 ` [Qemu-devel] [PATCH v2 03/17] target-alpha: Forget installed round mode after MT_FPCR Richard Henderson
2015-05-12 17:39 ` [Qemu-devel] [PATCH v2 04/17] target-alpha: Set PC correctly for floating-point exceptions Richard Henderson
2015-05-12 17:39 ` [Qemu-devel] [PATCH v2 05/17] target-alpha: Tidy FPCR representation Richard Henderson
2015-05-12 17:39 ` [Qemu-devel] [PATCH v2 06/17] target-alpha: Set fpcr_exc_status even for disabled exceptions Richard Henderson
2015-05-12 17:39 ` [Qemu-devel] [PATCH v2 07/17] target-alpha: Set EXC_M_SWC for exceptions from /S insns Richard Henderson
2015-05-12 17:39 ` [Qemu-devel] [PATCH v2 08/17] target-alpha: Raise IOV from CVTTQ Richard Henderson
2015-05-12 17:39 ` [Qemu-devel] [PATCH v2 09/17] target-alpha: Fix cvttq vs large integers Richard Henderson
2015-05-12 17:39 ` [Qemu-devel] [PATCH v2 10/17] target-alpha: Fix cvttq vs inf Richard Henderson
2015-05-12 17:39 ` [Qemu-devel] [PATCH v2 11/17] target-alpha: Fix integer overflow checking insns Richard Henderson
2015-05-12 17:39 ` [Qemu-devel] [PATCH v2 12/17] target-alpha: Implement WH64EN Richard Henderson
2015-05-12 17:39 ` [Qemu-devel] [PATCH v2 13/17] target-alpha: Disallow literal operand to 1C.30 to 1C.37 Richard Henderson
2015-05-12 17:39 ` Richard Henderson [this message]
2015-05-12 17:39 ` [Qemu-devel] [PATCH v2 15/17] target-alpha: Suppress underflow from CVTTQ if DNZ Richard Henderson
2015-05-12 17:39 ` [Qemu-devel] [PATCH v2 16/17] target-alpha: Raise IOV from CVTQL Richard Henderson
2015-05-12 17:39 ` [Qemu-devel] [PATCH v2 17/17] target-alpha: Rewrite helper_zapnot Richard Henderson
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