From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52166) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YsEAa-0007jU-S4 for qemu-devel@nongnu.org; Tue, 12 May 2015 13:40:41 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YsEAV-0007h3-VL for qemu-devel@nongnu.org; Tue, 12 May 2015 13:40:40 -0400 Received: from mail-qc0-x236.google.com ([2607:f8b0:400d:c01::236]:34045) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YsEAV-0007gv-Rl for qemu-devel@nongnu.org; Tue, 12 May 2015 13:40:35 -0400 Received: by qcyk17 with SMTP id k17so8636359qcy.1 for ; Tue, 12 May 2015 10:40:35 -0700 (PDT) Received: from anchor.com (50-194-63-110-static.hfc.comcastbusiness.net. [50.194.63.110]) by mx.google.com with ESMTPSA id f4sm13701736qhe.9.2015.05.12.10.40.34 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 12 May 2015 10:40:34 -0700 (PDT) Sender: Richard Henderson From: Richard Henderson Date: Tue, 12 May 2015 10:39:37 -0700 Message-Id: <1431452387-20280-8-git-send-email-rth@twiddle.net> In-Reply-To: <1431452387-20280-1-git-send-email-rth@twiddle.net> References: <1431452387-20280-1-git-send-email-rth@twiddle.net> Subject: [Qemu-devel] [PATCH v2 07/17] target-alpha: Set EXC_M_SWC for exceptions from /S insns List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Previously forgotten, the kernel needs the software completion bit to know that it needs to emulate software completion qualified insns. Reported-by: Al Viro Signed-off-by: Richard Henderson --- target-alpha/fpu_helper.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/target-alpha/fpu_helper.c b/target-alpha/fpu_helper.c index 6e84fd3..914c1d5 100644 --- a/target-alpha/fpu_helper.c +++ b/target-alpha/fpu_helper.c @@ -55,10 +55,8 @@ static uint32_t soft_to_fpcr_exc(CPUAlphaState *env) } static void fp_exc_raise1(CPUAlphaState *env, uintptr_t retaddr, - uint32_t exc, uint32_t regno) + uint32_t exc, uint32_t regno, uint32_t hw_exc) { - uint32_t hw_exc = 0; - hw_exc |= CONVERT_BIT(exc, FPCR_INV, EXC_M_INV); hw_exc |= CONVERT_BIT(exc, FPCR_DZE, EXC_M_DZE); hw_exc |= CONVERT_BIT(exc, FPCR_OVF, EXC_M_FOV); @@ -79,7 +77,7 @@ void helper_fp_exc_raise(CPUAlphaState *env, uint32_t ignore, uint32_t regno) env->fpcr |= exc; exc &= ~ignore; if (exc) { - fp_exc_raise1(env, GETPC(), exc, regno); + fp_exc_raise1(env, GETPC(), exc, regno, 0); } } } @@ -93,7 +91,7 @@ void helper_fp_exc_raise_s(CPUAlphaState *env, uint32_t ignore, uint32_t regno) exc &= ~ignore; if (exc) { exc &= env->fpcr_exc_enable; - fp_exc_raise1(env, GETPC(), exc, regno); + fp_exc_raise1(env, GETPC(), exc, regno, EXC_M_SWC); } } } -- 2.1.0