From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39815) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YsQg4-0006Y7-SZ for qemu-devel@nongnu.org; Wed, 13 May 2015 03:02:04 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YsQfz-00025f-Qx for qemu-devel@nongnu.org; Wed, 13 May 2015 03:02:00 -0400 Received: from mail-qc0-x235.google.com ([2607:f8b0:400d:c01::235]:34121) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YsQfz-00025V-LL for qemu-devel@nongnu.org; Wed, 13 May 2015 03:01:55 -0400 Received: by qcyk17 with SMTP id k17so17811472qcy.1 for ; Wed, 13 May 2015 00:01:55 -0700 (PDT) From: "Edgar E. Iglesias" Date: Wed, 13 May 2015 16:52:34 +1000 Message-Id: <1431499963-1019-10-git-send-email-edgar.iglesias@gmail.com> In-Reply-To: <1431499963-1019-1-git-send-email-edgar.iglesias@gmail.com> References: <1431499963-1019-1-git-send-email-edgar.iglesias@gmail.com> Subject: [Qemu-devel] [PATCH v1 09/18] target-arm: Add TLBI_ALLE1{IS} List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org, peter.maydell@linaro.org Cc: edgar.iglesias@xilinx.com, serge.fdrv@gmail.com, alex.bennee@linaro.org, agraf@suse.de, greg.bellows@linaro.org From: "Edgar E. Iglesias" Signed-off-by: Edgar E. Iglesias --- target-arm/helper.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/target-arm/helper.c b/target-arm/helper.c index ace933c..830c9d4 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -2366,6 +2366,14 @@ static const ARMCPRegInfo v8_cp_reginfo[] = { .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 2, .access = PL1_W, .type = ARM_CP_NOP }, /* TLBI operations */ + { .name = "TLBI_ALLE1", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 4, + .access = PL2_W, .type = ARM_CP_NO_RAW, + .writefn = tlbiall_write }, + { .name = "TLBI_ALLE1IS", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 4, + .access = PL2_W, .type = ARM_CP_NO_RAW, + .writefn = tlbiall_write }, { .name = "TLBI_VMALLE1IS", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0, .access = PL1_W, .type = ARM_CP_NO_RAW, -- 1.9.1