From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40650) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YsQix-0002ge-0L for qemu-devel@nongnu.org; Wed, 13 May 2015 03:05:03 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YsQir-0003m4-TF for qemu-devel@nongnu.org; Wed, 13 May 2015 03:04:58 -0400 Received: from mail-qk0-x22b.google.com ([2607:f8b0:400d:c09::22b]:33919) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YsQir-0003lw-Nu for qemu-devel@nongnu.org; Wed, 13 May 2015 03:04:53 -0400 Received: by qkgx75 with SMTP id x75so22404165qkg.1 for ; Wed, 13 May 2015 00:04:53 -0700 (PDT) From: "Edgar E. Iglesias" Date: Wed, 13 May 2015 16:52:39 +1000 Message-Id: <1431499963-1019-15-git-send-email-edgar.iglesias@gmail.com> In-Reply-To: <1431499963-1019-1-git-send-email-edgar.iglesias@gmail.com> References: <1431499963-1019-1-git-send-email-edgar.iglesias@gmail.com> Subject: [Qemu-devel] [PATCH v1 14/18] target-arm: Add CNTVOFF_EL2 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org, peter.maydell@linaro.org Cc: edgar.iglesias@xilinx.com, serge.fdrv@gmail.com, alex.bennee@linaro.org, agraf@suse.de, greg.bellows@linaro.org From: "Edgar E. Iglesias" Signed-off-by: Edgar E. Iglesias --- target-arm/cpu.h | 1 + target-arm/helper.c | 41 +++++++++++++++++++++++++++++++++++------ 2 files changed, 36 insertions(+), 6 deletions(-) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 6922e54..73a4ce8 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -355,6 +355,7 @@ typedef struct CPUARMState { }; uint64_t c14_cntfrq; /* Counter Frequency register */ uint64_t c14_cntkctl; /* Timer Control register */ + uint64_t cntvoff_el2; /* Counter Virtual Offset register */ ARMGenericTimer c14_timer[NUM_GTIMERS]; uint32_t c15_cpar; /* XScale Coprocessor Access Register */ uint32_t c15_ticonfig; /* TI925T configuration byte. */ diff --git a/target-arm/helper.c b/target-arm/helper.c index 5b7c195..380887a 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -1212,9 +1212,11 @@ static void gt_recalc_timer(ARMCPU *cpu, int timeridx) /* Timer enabled: calculate and set current ISTATUS, irq, and * reset timer to when ISTATUS next has to change */ + uint64_t offset = timeridx == GTIMER_VIRT ? + cpu->env.cp15.cntvoff_el2 : 0; uint64_t count = gt_get_countervalue(&cpu->env); /* Note that this must be unsigned 64 bit arithmetic: */ - int istatus = count >= gt->cval; + int istatus = (int64_t) (count - offset - gt->cval) >= 0; uint64_t nexttick; gt->ctl = deposit32(gt->ctl, 2, 1, istatus); @@ -1225,7 +1227,7 @@ static void gt_recalc_timer(ARMCPU *cpu, int timeridx) nexttick = UINT64_MAX; } else { /* Next transition is when we hit cval */ - nexttick = gt->cval; + nexttick = gt->cval + offset; } /* Note that the desired next expiry time might be beyond the * signed-64-bit range of a QEMUTimer -- in this case we just @@ -1257,6 +1259,11 @@ static uint64_t gt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri) return gt_get_countervalue(env); } +static uint64_t gt_virt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + return gt_get_countervalue(env) - env->cp15.cntvoff_el2; +} + static void gt_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { @@ -1269,17 +1276,19 @@ static void gt_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, static uint64_t gt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri) { int timeridx = ri->crm & 1; + uint64_t offset = timeridx == GTIMER_VIRT ? env->cp15.cntvoff_el2 : 0; return (uint32_t)(env->cp15.c14_timer[timeridx].cval - - gt_get_countervalue(env)); + gt_get_countervalue(env) - offset); } static void gt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { int timeridx = ri->crm & 1; + uint64_t offset = timeridx == GTIMER_VIRT ? env->cp15.cntvoff_el2 : 0; - env->cp15.c14_timer[timeridx].cval = gt_get_countervalue(env) + + env->cp15.c14_timer[timeridx].cval = gt_get_countervalue(env) - offset + sextract64(value, 0, 32); gt_recalc_timer(arm_env_get_cpu(env), timeridx); } @@ -1304,6 +1313,15 @@ static void gt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, } } +static void gt_cntvoff_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + ARMCPU *cpu = arm_env_get_cpu(env); + + raw_write(env, ri, value); + gt_recalc_timer(cpu, GTIMER_VIRT); +} + void arm_gt_ptimer_cb(void *opaque) { ARMCPU *cpu = opaque; @@ -1413,13 +1431,13 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = { { .name = "CNTVCT", .cp = 15, .crm = 14, .opc1 = 1, .access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_RAW | ARM_CP_IO, .accessfn = gt_vct_access, - .readfn = gt_cnt_read, .resetfn = arm_cp_reset_ignore, + .readfn = gt_virt_cnt_read, .resetfn = arm_cp_reset_ignore, }, { .name = "CNTVCT_EL0", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 2, .access = PL0_R, .type = ARM_CP_NO_RAW | ARM_CP_IO, .accessfn = gt_vct_access, - .readfn = gt_cnt_read, .resetfn = gt_cnt_reset, + .readfn = gt_virt_cnt_read, .resetfn = gt_cnt_reset, }, /* Comparison value, indicating when the timer goes off */ { .name = "CNTP_CVAL", .cp = 15, .crm = 14, .opc1 = 2, @@ -2553,6 +2571,10 @@ static const ARMCPRegInfo v8_el3_no_el2_cp_reginfo[] = { .opc0 = 3, .opc1 = 4, .opc2 = 2, .crn = 13, .crm = 0, .access = PL2_RW, .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore }, + { .name = "CNTVOFF_EL2", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 0, .opc2 = 3, + .access = PL2_RW, + .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore }, REGINFO_SENTINEL }; @@ -2661,6 +2683,13 @@ static const ARMCPRegInfo v8_el2_cp_reginfo[] = { .opc0 = 3, .opc1 = 4, .opc2 = 2, .crn = 13, .crm = 0, .access = PL2_RW, .resetvalue = 0, .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[2]) }, +#ifndef CONFIG_USER_ONLY + { .name = "CNTVOFF_EL2", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 0, .opc2 = 3, + .access = PL2_RW, + .writefn = gt_cntvoff_write, + .fieldoffset = offsetof(CPUARMState, cp15.cntvoff_el2) }, +#endif REGINFO_SENTINEL }; -- 1.9.1