From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40944) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YsQja-0003oV-U4 for qemu-devel@nongnu.org; Wed, 13 May 2015 03:05:40 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YsQjV-0004HN-Rs for qemu-devel@nongnu.org; Wed, 13 May 2015 03:05:38 -0400 Received: from mail-qk0-x233.google.com ([2607:f8b0:400d:c09::233]:33942) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YsQjR-0004GH-JC for qemu-devel@nongnu.org; Wed, 13 May 2015 03:05:32 -0400 Received: by qkgx75 with SMTP id x75so22410750qkg.1 for ; Wed, 13 May 2015 00:05:29 -0700 (PDT) From: "Edgar E. Iglesias" Date: Wed, 13 May 2015 16:52:40 +1000 Message-Id: <1431499963-1019-16-git-send-email-edgar.iglesias@gmail.com> In-Reply-To: <1431499963-1019-1-git-send-email-edgar.iglesias@gmail.com> References: <1431499963-1019-1-git-send-email-edgar.iglesias@gmail.com> Subject: [Qemu-devel] [PATCH v1 15/18] target-arm: Add CNTHCTL_EL2 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org, peter.maydell@linaro.org Cc: edgar.iglesias@xilinx.com, serge.fdrv@gmail.com, alex.bennee@linaro.org, agraf@suse.de, greg.bellows@linaro.org From: "Edgar E. Iglesias" Signed-off-by: Edgar E. Iglesias --- target-arm/cpu.h | 1 + target-arm/helper.c | 33 +++++++++++++++++++++++++++++++-- 2 files changed, 32 insertions(+), 2 deletions(-) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 73a4ce8..059c200 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -355,6 +355,7 @@ typedef struct CPUARMState { }; uint64_t c14_cntfrq; /* Counter Frequency register */ uint64_t c14_cntkctl; /* Timer Control register */ + uint32_t cnthctl_el2; /* Counter/Timer Hyp Control register */ uint64_t cntvoff_el2; /* Counter Virtual Offset register */ ARMGenericTimer c14_timer[NUM_GTIMERS]; uint32_t c15_cpar; /* XScale Coprocessor Access Register */ diff --git a/target-arm/helper.c b/target-arm/helper.c index 380887a..4c1d6c7 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -1155,8 +1155,18 @@ static CPAccessResult gt_cntfrq_access(CPUARMState *env, const ARMCPRegInfo *ri) static CPAccessResult gt_counter_access(CPUARMState *env, int timeridx) { + unsigned int cur_el = arm_current_el(env); + bool secure = arm_is_secure(env); + + if (arm_feature(env, ARM_FEATURE_EL2) && + timeridx == GTIMER_PHYS && !secure && cur_el < 2 && + !extract32(env->cp15.cnthctl_el2, 0, 1)) { + env->exception.target_el = 2; + return CP_ACCESS_TRAP; + } + /* CNT[PV]CT: not visible from PL0 if ELO[PV]CTEN is zero */ - if (arm_current_el(env) == 0 && + if (cur_el == 0 && !extract32(env->cp15.c14_cntkctl, timeridx, 1)) { env->exception.target_el = 1; return CP_ACCESS_TRAP; @@ -1166,10 +1176,21 @@ static CPAccessResult gt_counter_access(CPUARMState *env, int timeridx) static CPAccessResult gt_timer_access(CPUARMState *env, int timeridx) { + unsigned int cur_el = arm_current_el(env); + bool secure = arm_is_secure(env); + + if (arm_feature(env, ARM_FEATURE_EL2)) { + if (timeridx == GTIMER_PHYS && !secure && cur_el < 2 && + !extract32(env->cp15.cnthctl_el2, 1, 1)) { + env->exception.target_el = 2; + return CP_ACCESS_TRAP; + } + } + /* CNT[PV]_CVAL, CNT[PV]_CTL, CNT[PV]_TVAL: not visible from PL0 if * EL0[PV]TEN is zero. */ - if (arm_current_el(env) == 0 && + if (cur_el == 0 && !extract32(env->cp15.c14_cntkctl, 9 - timeridx, 1)) { env->exception.target_el = 1; return CP_ACCESS_TRAP; @@ -2571,6 +2592,10 @@ static const ARMCPRegInfo v8_el3_no_el2_cp_reginfo[] = { .opc0 = 3, .opc1 = 4, .opc2 = 2, .crn = 13, .crm = 0, .access = PL2_RW, .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore }, + { .name = "CNTHCTL_EL2", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 1, .opc2 = 0, + .access = PL2_RW, + .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore, }, { .name = "CNTVOFF_EL2", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 0, .opc2 = 3, .access = PL2_RW, @@ -2684,6 +2709,10 @@ static const ARMCPRegInfo v8_el2_cp_reginfo[] = { .access = PL2_RW, .resetvalue = 0, .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[2]) }, #ifndef CONFIG_USER_ONLY + { .name = "CNTHCTL_EL2", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 1, .opc2 = 0, + .access = PL2_RW, + .fieldoffset = offsetof(CPUARMState, cp15.cnthctl_el2) }, { .name = "CNTVOFF_EL2", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 0, .opc2 = 3, .access = PL2_RW, -- 1.9.1