From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39286) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YsQeI-0003Y1-Ks for qemu-devel@nongnu.org; Wed, 13 May 2015 03:00:16 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YsQeE-0001Mi-T8 for qemu-devel@nongnu.org; Wed, 13 May 2015 03:00:10 -0400 Received: from mail-oi0-x22a.google.com ([2607:f8b0:4003:c06::22a]:33951) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YsQeE-0001Lt-OI for qemu-devel@nongnu.org; Wed, 13 May 2015 03:00:06 -0400 Received: by oiko83 with SMTP id o83so24284551oik.1 for ; Wed, 13 May 2015 00:00:06 -0700 (PDT) From: "Edgar E. Iglesias" Date: Wed, 13 May 2015 16:52:31 +1000 Message-Id: <1431499963-1019-7-git-send-email-edgar.iglesias@gmail.com> In-Reply-To: <1431499963-1019-1-git-send-email-edgar.iglesias@gmail.com> References: <1431499963-1019-1-git-send-email-edgar.iglesias@gmail.com> Subject: [Qemu-devel] [PATCH v1 06/18] target-arm: Add TCR_EL2 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org, peter.maydell@linaro.org Cc: edgar.iglesias@xilinx.com, serge.fdrv@gmail.com, alex.bennee@linaro.org, agraf@suse.de, greg.bellows@linaro.org From: "Edgar E. Iglesias" Signed-off-by: Edgar E. Iglesias --- target-arm/helper.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/target-arm/helper.c b/target-arm/helper.c index 168549c..025e334 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -2524,6 +2524,10 @@ static const ARMCPRegInfo v8_el3_no_el2_cp_reginfo[] = { .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 0, .access = PL2_RW, .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore }, + { .name = "TCR_EL2", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 2, + .access = PL2_RW, + .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore }, REGINFO_SENTINEL }; @@ -2603,6 +2607,11 @@ static const ARMCPRegInfo v8_el2_cp_reginfo[] = { .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 0, .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.mair_el[2]), .resetvalue = 0 }, + { .name = "TCR_EL2", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 2, + .access = PL2_RW, .writefn = vmsa_tcr_el1_write, + .resetfn = vmsa_ttbcr_reset, .raw_writefn = raw_write, + .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[2]) }, REGINFO_SENTINEL }; -- 1.9.1