From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39422) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YsQev-0004Qe-OP for qemu-devel@nongnu.org; Wed, 13 May 2015 03:00:50 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YsQeo-0001gy-MI for qemu-devel@nongnu.org; Wed, 13 May 2015 03:00:49 -0400 Received: from mail-oi0-x22c.google.com ([2607:f8b0:4003:c06::22c]:33994) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YsQeo-0001gm-Ii for qemu-devel@nongnu.org; Wed, 13 May 2015 03:00:42 -0400 Received: by oiko83 with SMTP id o83so24295167oik.1 for ; Wed, 13 May 2015 00:00:42 -0700 (PDT) From: "Edgar E. Iglesias" Date: Wed, 13 May 2015 16:52:32 +1000 Message-Id: <1431499963-1019-8-git-send-email-edgar.iglesias@gmail.com> In-Reply-To: <1431499963-1019-1-git-send-email-edgar.iglesias@gmail.com> References: <1431499963-1019-1-git-send-email-edgar.iglesias@gmail.com> Subject: [Qemu-devel] [PATCH v1 07/18] target-arm: Add SCTLR_EL2 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org, peter.maydell@linaro.org Cc: edgar.iglesias@xilinx.com, serge.fdrv@gmail.com, alex.bennee@linaro.org, agraf@suse.de, greg.bellows@linaro.org From: "Edgar E. Iglesias" Signed-off-by: Edgar E. Iglesias --- target-arm/helper.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/target-arm/helper.c b/target-arm/helper.c index 025e334..c44cbb4 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -2528,6 +2528,10 @@ static const ARMCPRegInfo v8_el3_no_el2_cp_reginfo[] = { .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 2, .access = PL2_RW, .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore }, + { .name = "SCTLR_EL2", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 0, + .access = PL2_RW, + .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore }, REGINFO_SENTINEL }; @@ -2612,6 +2616,10 @@ static const ARMCPRegInfo v8_el2_cp_reginfo[] = { .access = PL2_RW, .writefn = vmsa_tcr_el1_write, .resetfn = vmsa_ttbcr_reset, .raw_writefn = raw_write, .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[2]) }, + { .name = "SCTLR_EL2", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 0, + .access = PL2_RW, .raw_writefn = raw_write, .writefn = sctlr_write, + .fieldoffset = offsetof(CPUARMState, cp15.sctlr_el[2]) }, REGINFO_SENTINEL }; -- 1.9.1