From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39561) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YsQfT-0005Ib-Kl for qemu-devel@nongnu.org; Wed, 13 May 2015 03:01:24 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YsQfO-0001sM-Ji for qemu-devel@nongnu.org; Wed, 13 May 2015 03:01:23 -0400 Received: from mail-ob0-x22d.google.com ([2607:f8b0:4003:c01::22d]:36061) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YsQfO-0001sE-9b for qemu-devel@nongnu.org; Wed, 13 May 2015 03:01:18 -0400 Received: by obbkp3 with SMTP id kp3so23053974obb.3 for ; Wed, 13 May 2015 00:01:17 -0700 (PDT) From: "Edgar E. Iglesias" Date: Wed, 13 May 2015 16:52:33 +1000 Message-Id: <1431499963-1019-9-git-send-email-edgar.iglesias@gmail.com> In-Reply-To: <1431499963-1019-1-git-send-email-edgar.iglesias@gmail.com> References: <1431499963-1019-1-git-send-email-edgar.iglesias@gmail.com> Subject: [Qemu-devel] [PATCH v1 08/18] target-arm: Add TTBR0_EL2 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org, peter.maydell@linaro.org Cc: edgar.iglesias@xilinx.com, serge.fdrv@gmail.com, alex.bennee@linaro.org, agraf@suse.de, greg.bellows@linaro.org From: "Edgar E. Iglesias" Signed-off-by: Edgar E. Iglesias --- target-arm/helper.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/target-arm/helper.c b/target-arm/helper.c index c44cbb4..ace933c 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -2532,6 +2532,10 @@ static const ARMCPRegInfo v8_el3_no_el2_cp_reginfo[] = { .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 0, .access = PL2_RW, .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore }, + { .name = "TTBR0_EL2", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 0, + .access = PL2_RW, + .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore }, REGINFO_SENTINEL }; @@ -2620,6 +2624,10 @@ static const ARMCPRegInfo v8_el2_cp_reginfo[] = { .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 0, .access = PL2_RW, .raw_writefn = raw_write, .writefn = sctlr_write, .fieldoffset = offsetof(CPUARMState, cp15.sctlr_el[2]) }, + { .name = "TTBR0_EL2", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 0, + .access = PL2_RW, .writefn = vmsa_ttbr_write, .resetvalue = 0, + .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el[2]) }, REGINFO_SENTINEL }; -- 1.9.1