[Qemu-devel] [PATCH 09/10] target-tricore: add FRET instructions of the v1.6 ISA

[Bastian Koppelmann <kbastian@mail.uni-paderborn.de>]

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
---
 target-tricore/translate.c       | 14 ++++++++++++++
 target-tricore/tricore-opcodes.h |  2 ++
 2 files changed, 16 insertions(+)

diff --git a/target-tricore/translate.c b/target-tricore/translate.c
index 545cc06..4f517b3 100644
--- a/target-tricore/translate.c
+++ b/target-tricore/translate.c
@@ -3282,6 +3282,15 @@ static void gen_fcall_save_ctx(DisasContext *ctx)
     tcg_gen_movi_tl(cpu_gpr_a[11], ctx->next_pc);
 }
 
+static void gen_fret(DisasContext *ctx)
+{
+    tcg_gen_andi_tl(cpu_PC, cpu_gpr_a[11], ~0x1);
+    tcg_gen_qemu_ld_tl(cpu_gpr_a[11], cpu_gpr_a[10], ctx->mem_idx, MO_LESL);
+    tcg_gen_addi_tl(cpu_gpr_a[10], cpu_gpr_a[10], 4);
+    tcg_gen_exit_tb(0);
+    ctx->bstate = BS_BRANCH;
+}
+
 static void gen_compute_branch(DisasContext *ctx, uint32_t opc, int r1,
                                int r2 , int32_t constant , int32_t offset)
 {
@@ -3864,6 +3873,8 @@ static void decode_sr_system(CPUTriCoreState *env, DisasContext *ctx)
     case OPC2_16_SR_DEBUG:
         /* raise EXCP_DEBUG */
         break;
+    case OPC2_16_SR_FRET:
+        gen_fret(ctx);
     }
 }
 
@@ -7837,6 +7848,9 @@ static void decode_sys_interrupts(CPUTriCoreState *env, DisasContext *ctx)
     case OPC2_32_SYS_RET:
         gen_compute_branch(ctx, op2, 0, 0, 0, 0);
         break;
+    case OPC2_32_SYS_FRET:
+        gen_fret(ctx);
+        break;
     case OPC2_32_SYS_RFE:
         gen_helper_rfe(cpu_env);
         tcg_gen_exit_tb(0);
diff --git a/target-tricore/tricore-opcodes.h b/target-tricore/tricore-opcodes.h
index bb1939c..22c79f5 100644
--- a/target-tricore/tricore-opcodes.h
+++ b/target-tricore/tricore-opcodes.h
@@ -399,6 +399,7 @@ enum {
     OPC2_16_SR_RET                                   = 0x09,
     OPC2_16_SR_RFE                                   = 0x08,
     OPC2_16_SR_DEBUG                                 = 0x0a,
+    OPC2_16_SR_FRET                                  = 0x07,
 };
 /* OPCM_16_SR_ACCU                                   */
 enum {
@@ -1438,4 +1439,5 @@ enum {
     OPC2_32_SYS_TRAPSV                           = 0x15,
     OPC2_32_SYS_TRAPV                            = 0x14,
     OPC2_32_SYS_RESTORE                          = 0x0e,
+    OPC2_32_SYS_FRET                             = 0x03,
 };
-- 
2.4.0