From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39395) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YsTEP-0008QZ-Lt for qemu-devel@nongnu.org; Wed, 13 May 2015 05:45:46 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YsTEB-0001QX-Iy for qemu-devel@nongnu.org; Wed, 13 May 2015 05:45:37 -0400 Received: from mail.uni-paderborn.de ([131.234.142.9]:57617) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YsTEB-0001Le-Bh for qemu-devel@nongnu.org; Wed, 13 May 2015 05:45:23 -0400 From: Bastian Koppelmann Date: Wed, 13 May 2015 11:45:09 +0200 Message-Id: <1431510311-13355-9-git-send-email-kbastian@mail.uni-paderborn.de> In-Reply-To: <1431510311-13355-1-git-send-email-kbastian@mail.uni-paderborn.de> References: <1431510311-13355-1-git-send-email-kbastian@mail.uni-paderborn.de> Subject: [Qemu-devel] [PATCH 08/10] target-tricore: add FCALL instructions of the v1.6 ISA List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: rth@twiddle.net Signed-off-by: Bastian Koppelmann --- target-tricore/translate.c | 21 +++++++++++++++++++++ target-tricore/tricore-opcodes.h | 3 +++ 2 files changed, 24 insertions(+) diff --git a/target-tricore/translate.c b/target-tricore/translate.c index 4aea0c6..545cc06 100644 --- a/target-tricore/translate.c +++ b/target-tricore/translate.c @@ -3275,6 +3275,13 @@ static void gen_loop(DisasContext *ctx, int r1, int32_t offset) gen_goto_tb(ctx, 0, ctx->next_pc); } +static void gen_fcall_save_ctx(DisasContext *ctx) +{ + tcg_gen_addi_tl(cpu_gpr_a[10], cpu_gpr_a[10], -4); + tcg_gen_qemu_st_tl(cpu_gpr_a[11], cpu_gpr_a[10], ctx->mem_idx, MO_LESL); + tcg_gen_movi_tl(cpu_gpr_a[11], ctx->next_pc); +} + static void gen_compute_branch(DisasContext *ctx, uint32_t opc, int r1, int r2 , int32_t constant , int32_t offset) { @@ -3369,6 +3376,14 @@ static void gen_compute_branch(DisasContext *ctx, uint32_t opc, int r1, gen_helper_1arg(call, ctx->next_pc); gen_goto_tb(ctx, 0, EA_B_ABSOLUT(offset)); break; + case OPC1_32_B_FCALL: + gen_fcall_save_ctx(ctx); + gen_goto_tb(ctx, 0, ctx->pc + offset * 2); + break; + case OPC1_32_B_FCALLA: + gen_fcall_save_ctx(ctx); + gen_goto_tb(ctx, 0, EA_B_ABSOLUT(offset)); + break; case OPC1_32_B_JLA: tcg_gen_movi_tl(cpu_gpr_a[11], ctx->next_pc); /* fall through */ @@ -6311,6 +6326,10 @@ static void decode_rr_idirect(CPUTriCoreState *env, DisasContext *ctx) gen_helper_1arg(call, ctx->next_pc); tcg_gen_andi_tl(cpu_PC, cpu_gpr_a[r1], ~0x1); break; + case OPC2_32_RR_FCALLI: + gen_fcall_save_ctx(ctx); + tcg_gen_andi_tl(cpu_PC, cpu_gpr_a[r1], ~0x1); + break; } tcg_gen_exit_tb(0); ctx->bstate = BS_BRANCH; @@ -7946,6 +7965,8 @@ static void decode_32Bit_opc(CPUTriCoreState *env, DisasContext *ctx) /* B-format */ case OPC1_32_B_CALL: case OPC1_32_B_CALLA: + case OPC1_32_B_FCALL: + case OPC1_32_B_FCALLA: case OPC1_32_B_J: case OPC1_32_B_JA: case OPC1_32_B_JL: diff --git a/target-tricore/tricore-opcodes.h b/target-tricore/tricore-opcodes.h index d1506a9..bb1939c 100644 --- a/target-tricore/tricore-opcodes.h +++ b/target-tricore/tricore-opcodes.h @@ -428,6 +428,8 @@ enum { /* B Format */ OPC1_32_B_CALL = 0x6d, OPC1_32_B_CALLA = 0xed, + OPC1_32_B_FCALL = 0x61, + OPC1_32_B_FCALLA = 0xe1, OPC1_32_B_J = 0x1d, OPC1_32_B_JA = 0x9d, OPC1_32_B_JL = 0x5d, @@ -1127,6 +1129,7 @@ enum { OPC2_32_RR_JI = 0x03, OPC2_32_RR_JLI = 0x02, OPC2_32_RR_CALLI = 0x00, + OPC2_32_RR_FCALLI = 0x01, }; /* * RR1 Format -- 2.4.0