From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [Qemu-devel] [PULL 05/21] arm: xlnx-zynqmp: Connect CPU Timers to GIC
Date: Mon, 18 May 2015 20:15:05 +0100 [thread overview]
Message-ID: <1431976521-30352-6-git-send-email-peter.maydell@linaro.org> (raw)
In-Reply-To: <1431976521-30352-1-git-send-email-peter.maydell@linaro.org>
From: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Connect the GPIO outputs from the individual CPUs for the timers to the
GIC.
Tested-by: Alistair Francis <alistair.francis@xilinx.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Message-id: a7866a4f0c903c91fa3034210b4d2879aa4bfcb9.1431381507.git.peter.crosthwaite@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/arm/xlnx-zynqmp.c | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c
index d4c5309..f98e9f7 100644
--- a/hw/arm/xlnx-zynqmp.c
+++ b/hw/arm/xlnx-zynqmp.c
@@ -16,10 +16,14 @@
*/
#include "hw/arm/xlnx-zynqmp.h"
+#include "hw/intc/arm_gic_common.h"
#include "exec/address-spaces.h"
#define GIC_NUM_SPI_INTR 160
+#define ARM_PHYS_TIMER_PPI 30
+#define ARM_VIRT_TIMER_PPI 27
+
#define GIC_BASE_ADDR 0xf9000000
#define GIC_DIST_ADDR 0xf9010000
#define GIC_CPU_ADDR 0xf9020000
@@ -34,6 +38,11 @@ static const XlnxZynqMPGICRegion xlnx_zynqmp_gic_regions[] = {
{ .region_index = 1, .address = GIC_CPU_ADDR, },
};
+static inline int arm_gic_ppi_index(int cpu_nr, int ppi_index)
+{
+ return GIC_NUM_SPI_INTR + cpu_nr * GIC_INTERNAL + ppi_index;
+}
+
static void xlnx_zynqmp_init(Object *obj)
{
XlnxZynqMPState *s = XLNX_ZYNQMP(obj);
@@ -86,6 +95,8 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
}
for (i = 0; i < XLNX_ZYNQMP_NUM_CPUS; i++) {
+ qemu_irq irq;
+
object_property_set_int(OBJECT(&s->cpu[i]), QEMU_PSCI_CONDUIT_SMC,
"psci-conduit", &error_abort);
if (i > 0) {
@@ -109,6 +120,12 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i,
qdev_get_gpio_in(DEVICE(&s->cpu[i]), ARM_CPU_IRQ));
+ irq = qdev_get_gpio_in(DEVICE(&s->gic),
+ arm_gic_ppi_index(i, ARM_PHYS_TIMER_PPI));
+ qdev_connect_gpio_out(DEVICE(&s->cpu[i]), 0, irq);
+ irq = qdev_get_gpio_in(DEVICE(&s->gic),
+ arm_gic_ppi_index(i, ARM_VIRT_TIMER_PPI));
+ qdev_connect_gpio_out(DEVICE(&s->cpu[i]), 1, irq);
}
}
--
1.9.1
next prev parent reply other threads:[~2015-05-18 19:15 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-05-18 19:15 [Qemu-devel] [PULL 00/21] target-arm queue Peter Maydell
2015-05-18 19:15 ` [Qemu-devel] [PULL 01/21] target-arm: cpu64: generalise name of A57 regs Peter Maydell
2015-05-18 19:15 ` [Qemu-devel] [PULL 02/21] target-arm: cpu64: Add support for Cortex-A53 Peter Maydell
2015-05-18 19:15 ` [Qemu-devel] [PULL 03/21] arm: Introduce Xilinx ZynqMP SoC Peter Maydell
2015-05-18 19:15 ` [Qemu-devel] [PULL 04/21] arm: xlnx-zynqmp: Add GIC Peter Maydell
2015-05-18 19:15 ` Peter Maydell [this message]
2015-05-18 19:15 ` [Qemu-devel] [PULL 06/21] net: cadence_gem: Clean up variable names Peter Maydell
2015-05-18 19:15 ` [Qemu-devel] [PULL 07/21] net: cadence_gem: Split state struct and type into header Peter Maydell
2015-05-18 19:15 ` [Qemu-devel] [PULL 08/21] arm: xlnx-zynqmp: Add GEM support Peter Maydell
2015-05-18 19:15 ` [Qemu-devel] [PULL 09/21] char: cadence_uart: Clean up variable names Peter Maydell
2015-05-18 19:15 ` [Qemu-devel] [PULL 10/21] char: cadence_uart: Split state struct and type into header Peter Maydell
2015-05-18 19:15 ` [Qemu-devel] [PULL 11/21] arm: xlnx-zynqmp: Add UART support Peter Maydell
2015-05-18 19:15 ` [Qemu-devel] [PULL 12/21] arm: Add xlnx-ep108 machine Peter Maydell
2015-05-18 19:15 ` [Qemu-devel] [PULL 13/21] arm: xlnx-ep108: Add external RAM Peter Maydell
2015-05-18 19:15 ` [Qemu-devel] [PULL 14/21] arm: xlnx-ep108: Add bootloading Peter Maydell
2015-05-18 19:15 ` [Qemu-devel] [PULL 15/21] linux-user/arm: Correct TARGET_NR_timerfd to TARGET_NR_timerfd_create Peter Maydell
2015-05-18 19:15 ` [Qemu-devel] [PULL 16/21] target-arm: Add TTBR regime function and use Peter Maydell
2015-05-18 19:15 ` [Qemu-devel] [PULL 17/21] target-arm: Add EL3 and EL2 TCR checking Peter Maydell
2015-05-18 19:15 ` [Qemu-devel] [PULL 18/21] target-arm: Add WFx syndrome function Peter Maydell
2015-05-18 19:15 ` [Qemu-devel] [PULL 19/21] target-arm: Correct accessfn for CNTP_{CT}VAL_EL0 Peter Maydell
2015-05-18 19:15 ` [Qemu-devel] [PULL 20/21] target-arm: Correct accessfn for CNTV_TVAL_EL0 Peter Maydell
2015-05-18 19:15 ` [Qemu-devel] [PULL 21/21] target-arm: Remove unneeded '+' Peter Maydell
2015-05-19 7:57 ` [Qemu-devel] [PULL 00/21] target-arm queue Peter Maydell
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1431976521-30352-6-git-send-email-peter.maydell@linaro.org \
--to=peter.maydell@linaro.org \
--cc=qemu-devel@nongnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).