From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58916) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YujZL-00087U-Bs for qemu-devel@nongnu.org; Tue, 19 May 2015 11:36:40 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YujZG-0001wg-KL for qemu-devel@nongnu.org; Tue, 19 May 2015 11:36:35 -0400 From: Kevin Wolf Date: Tue, 19 May 2015 17:36:02 +0200 Message-Id: <1432049762-2184-9-git-send-email-kwolf@redhat.com> In-Reply-To: <1432049762-2184-1-git-send-email-kwolf@redhat.com> References: <1432049762-2184-1-git-send-email-kwolf@redhat.com> Subject: [Qemu-devel] [PATCH 8/8] fdc-test: Test state for existing cases more thoroughly List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-block@nongnu.org Cc: kwolf@redhat.com, jsnow@redhat.com, qemu-devel@nongnu.org This just adds a few additional checks of the MSR and interrupt pin to the already existing test cases. Signed-off-by: Kevin Wolf --- tests/fdc-test.c | 34 ++++++++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/tests/fdc-test.c b/tests/fdc-test.c index 3c6c83c..416394f 100644 --- a/tests/fdc-test.c +++ b/tests/fdc-test.c @@ -218,6 +218,10 @@ static uint8_t send_read_no_dma_command(int nb_sect, uint8_t expected_st0) inb(FLOPPY_BASE + reg_fifo); } + msr = inb(FLOPPY_BASE + reg_msr); + assert_bit_set(msr, BUSY | RQM | DIO); + g_assert(get_irq(FLOPPY_IRQ)); + st0 = floppy_recv(); if (st0 != expected_st0) { ret = 1; @@ -228,8 +232,15 @@ static uint8_t send_read_no_dma_command(int nb_sect, uint8_t expected_st0) floppy_recv(); floppy_recv(); floppy_recv(); + g_assert(get_irq(FLOPPY_IRQ)); floppy_recv(); + /* Check that we're back in command phase */ + msr = inb(FLOPPY_BASE + reg_msr); + assert_bit_clear(msr, BUSY | DIO); + assert_bit_set(msr, RQM); + g_assert(!get_irq(FLOPPY_IRQ)); + return ret; } @@ -403,6 +414,7 @@ static void test_read_id(void) uint8_t head = 0; uint8_t cyl; uint8_t st0; + uint8_t msr; /* Seek to track 0 and check with READ ID */ send_seek(0); @@ -411,18 +423,29 @@ static void test_read_id(void) g_assert(!get_irq(FLOPPY_IRQ)); floppy_send(head << 2 | drive); + msr = inb(FLOPPY_BASE + reg_msr); + if (!get_irq(FLOPPY_IRQ)) { + assert_bit_set(msr, BUSY); + assert_bit_clear(msr, RQM); + } + while (!get_irq(FLOPPY_IRQ)) { /* qemu involves a timer with READ ID... */ clock_step(1000000000LL / 50); } + msr = inb(FLOPPY_BASE + reg_msr); + assert_bit_set(msr, BUSY | RQM | DIO); + st0 = floppy_recv(); floppy_recv(); floppy_recv(); cyl = floppy_recv(); head = floppy_recv(); floppy_recv(); + g_assert(get_irq(FLOPPY_IRQ)); floppy_recv(); + g_assert(!get_irq(FLOPPY_IRQ)); g_assert_cmpint(cyl, ==, 0); g_assert_cmpint(head, ==, 0); @@ -443,18 +466,29 @@ static void test_read_id(void) g_assert(!get_irq(FLOPPY_IRQ)); floppy_send(head << 2 | drive); + msr = inb(FLOPPY_BASE + reg_msr); + if (!get_irq(FLOPPY_IRQ)) { + assert_bit_set(msr, BUSY); + assert_bit_clear(msr, RQM); + } + while (!get_irq(FLOPPY_IRQ)) { /* qemu involves a timer with READ ID... */ clock_step(1000000000LL / 50); } + msr = inb(FLOPPY_BASE + reg_msr); + assert_bit_set(msr, BUSY | RQM | DIO); + st0 = floppy_recv(); floppy_recv(); floppy_recv(); cyl = floppy_recv(); head = floppy_recv(); floppy_recv(); + g_assert(get_irq(FLOPPY_IRQ)); floppy_recv(); + g_assert(!get_irq(FLOPPY_IRQ)); g_assert_cmpint(cyl, ==, 8); g_assert_cmpint(head, ==, 1); -- 1.8.3.1