[Qemu-devel] [PATCH v2 00/10] TriCore v1.6.1 ISA and missing v1.6 instructions

[Bastian Koppelmann <kbastian@mail.uni-paderborn.de>]

Hi,

the new Aurix platform introduces a new ISA version, so this patchset
adds a new feature bit and changes the generic Aurix cpu to a more specific
tc27x cpu model. While at this, it introduces a new cpu model tc1797 which
uses the v1.3.1 ISA and fixes the tc1796 to us the v1.3 ISA.

It also adds the with v1.6.1 introduces instructions cmpswap, swapmsk and
crc32. While at this, it adds the missing instructions of the v1.6 ISA.

Cheers,
Bastian

v1->v2:
    - FRET and FCALL don't create a wrong register state anymore, if the load traps.

Bastian Koppelmann (10):
  target-tricore: Add ISA v1.3.1 cpu and fix tc1796 to using v1.3
  target-tricore: introduce ISA v1.6.1 feature
  target-tricore: Add SRC_MOV_E instruction of the v1.6 ISA
  target-tricore: add CMPSWP instructions of the v1.6.1 ISA
  target-tricore: add SWAPMSK instructions of the v1.6.1 ISA
  target-tricore: add RR_CRC32 instruction of the v1.6.1 ISA
  target-tricore: add SYS_RESTORE instruction of the v1.6 ISA
  target-tricore: add FCALL instructions of the v1.6 ISA
  target-tricore: add FRET instructions of the v1.6 ISA
  target-tricore: add RR_DIV and RR_DIV_U instructions of the v1.6 ISA

 target-tricore/cpu.c             |  18 ++++-
 target-tricore/cpu.h             |   1 +
 target-tricore/helper.h          |   4 +
 target-tricore/op_helper.c       |  60 ++++++++++++++
 target-tricore/translate.c       | 166 ++++++++++++++++++++++++++++++++++++++-
 target-tricore/tricore-opcodes.h |  19 +++++
 6 files changed, 263 insertions(+), 5 deletions(-)

-- 
2.4.1