[Qemu-devel] [PATCH 0/3] TriCore bugfixes

[Qemu-devel] [PATCH 0/3] TriCore bugfixes

[Bastian Koppelmann]

Hi,

while testing the new v1.6.1 instructions I found three bugs in the old
instructions.

Cheers,
Bastian 

Bastian Koppelmann (3):
  target-tricore: fix OPC2_32_RR_DVINIT_HU having write before use on
    the result
  target-tricore: fix msub32_q producing the wrong overflow bit
  target-tricore: fix BOL_ST_H_LONGOFF using ld

 target-tricore/translate.c | 15 ++-------------
 1 file changed, 2 insertions(+), 13 deletions(-)

-- 
2.4.1

[Qemu-devel] [PATCH 1/3] target-tricore: fix OPC2_32_RR_DVINIT_HU having write before use on the result

[Bastian Koppelmann]

If the argument r1 was the same as the extended result register r3+1, we would
overwrite r1 and then use it.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
---
 target-tricore/translate.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target-tricore/translate.c b/target-tricore/translate.c
index 663b2a0..4b935fd 100644
--- a/target-tricore/translate.c
+++ b/target-tricore/translate.c
@@ -6321,8 +6321,8 @@ static void decode_rr_divide(CPUTriCoreState *env, DisasContext *ctx)
         /* sv */
         tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
         /* write result */
-        tcg_gen_mov_tl(cpu_gpr_d[r3+1], temp3);
         tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], 16);
+        tcg_gen_mov_tl(cpu_gpr_d[r3+1], temp3);
         tcg_temp_free(temp);
         tcg_temp_free(temp2);
         tcg_temp_free(temp3);
-- 
2.4.1

[Qemu-devel] [PATCH 2/3] target-tricore: fix msub32_q producing the wrong overflow bit

[Bastian Koppelmann]

The inversion of the overflow bit as a special case, which was needed for the
madd32_q instructions, does not apply for msub32_q instructions. So remove it.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
---
 target-tricore/translate.c | 11 -----------
 1 file changed, 11 deletions(-)

diff --git a/target-tricore/translate.c b/target-tricore/translate.c
index 4b935fd..2d886e6 100644
--- a/target-tricore/translate.c
+++ b/target-tricore/translate.c
@@ -1938,17 +1938,6 @@ gen_msub32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n,
     tcg_gen_or_i64(t1, t1, t2);
     tcg_gen_trunc_i64_i32(cpu_PSW_V, t1);
     tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
-    /* We produce an overflow on the host if the mul before was
-       (0x80000000 * 0x80000000) << 1). If this is the
-       case, we negate the ovf. */
-    if (n == 1) {
-        tcg_gen_setcondi_tl(TCG_COND_EQ, temp, arg2, 0x80000000);
-        tcg_gen_setcond_tl(TCG_COND_EQ, temp2, arg2, arg3);
-        tcg_gen_and_tl(temp, temp, temp2);
-        tcg_gen_shli_tl(temp, temp, 31);
-        /* negate v bit, if special condition */
-        tcg_gen_xor_tl(cpu_PSW_V, cpu_PSW_V, temp);
-    }
     /* Calc SV bit */
     tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
     /* Calc AV/SAV bits */
-- 
2.4.1

[Qemu-devel] [PATCH 3/3] target-tricore: fix BOL_ST_H_LONGOFF using ld

[Bastian Koppelmann]

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
---
 target-tricore/translate.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target-tricore/translate.c b/target-tricore/translate.c
index 2d886e6..bf11ed4 100644
--- a/target-tricore/translate.c
+++ b/target-tricore/translate.c
@@ -5150,7 +5150,7 @@ static void decode_bol_opc(CPUTriCoreState *env, DisasContext *ctx, int32_t op1)
         break;
     case OPC1_32_BOL_ST_H_LONGOFF:
         if (tricore_feature(env, TRICORE_FEATURE_16)) {
-            gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_LESW);
+            gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_LESW);
         } else {
             /* raise illegal opcode trap */
         }
-- 
2.4.1