From: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
To: qemu-devel@nongnu.org
Subject: [Qemu-devel] [PULL 00/10] tricore-patches
Date: Fri, 22 May 2015 17:05:58 +0200 [thread overview]
Message-ID: <1432307168-10401-1-git-send-email-kbastian@mail.uni-paderborn.de> (raw)
The following changes since commit 8b6db32a4ec47d1171ccfa21d557096b99f4eef0:
Merge remote-tracking branch 'remotes/stefanha/tags/block-pull-request' into staging (2015-05-22 13:25:40 +0100)
are available in the git repository at:
https://github.com/bkoppelmann/qemu-tricore-upstream.git tags/pull-tricore-20150522
for you to fetch changes up to 9371557115a734412974f8d4096cbe8a62ca2731:
target-tricore: add RR_DIV and RR_DIV_U instructions of the v1.6 ISA (2015-05-22 17:02:34 +0200)
----------------------------------------------------------------
TriCore v1.6.1 ISA and missing v1.6 instructions
----------------------------------------------------------------
Bastian Koppelmann (10):
target-tricore: Add ISA v1.3.1 cpu and fix tc1796 to using v1.3
target-tricore: introduce ISA v1.6.1 feature
target-tricore: Add SRC_MOV_E instruction of the v1.6 ISA
target-tricore: add CMPSWP instructions of the v1.6.1 ISA
target-tricore: add SWAPMSK instructions of the v1.6.1 ISA
target-tricore: add RR_CRC32 instruction of the v1.6.1 ISA
target-tricore: add SYS_RESTORE instruction of the v1.6 ISA
target-tricore: add FCALL instructions of the v1.6 ISA
target-tricore: add FRET instructions of the v1.6 ISA
target-tricore: add RR_DIV and RR_DIV_U instructions of the v1.6 ISA
target-tricore/cpu.c | 18 ++++-
target-tricore/cpu.h | 1 +
target-tricore/helper.h | 4 +
target-tricore/op_helper.c | 60 ++++++++++++++
target-tricore/translate.c | 166 ++++++++++++++++++++++++++++++++++++++-
target-tricore/tricore-opcodes.h | 19 +++++
6 files changed, 263 insertions(+), 5 deletions(-)
--
2.4.1
next reply other threads:[~2015-05-22 15:06 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-05-22 15:05 Bastian Koppelmann [this message]
2015-05-22 15:05 ` [Qemu-devel] [PULL 01/10] target-tricore: Add ISA v1.3.1 cpu and fix tc1796 to using v1.3 Bastian Koppelmann
2015-05-22 15:06 ` [Qemu-devel] [PULL 02/10] target-tricore: introduce ISA v1.6.1 feature Bastian Koppelmann
2015-05-22 15:06 ` [Qemu-devel] [PULL 03/10] target-tricore: Add SRC_MOV_E instruction of the v1.6 ISA Bastian Koppelmann
2015-05-22 15:06 ` [Qemu-devel] [PULL 04/10] target-tricore: add CMPSWP instructions of the v1.6.1 ISA Bastian Koppelmann
2015-05-22 15:06 ` [Qemu-devel] [PULL 05/10] target-tricore: add SWAPMSK " Bastian Koppelmann
2015-05-22 15:06 ` [Qemu-devel] [PULL 06/10] target-tricore: add RR_CRC32 instruction " Bastian Koppelmann
2015-05-22 15:06 ` [Qemu-devel] [PULL 07/10] target-tricore: add SYS_RESTORE instruction of the v1.6 ISA Bastian Koppelmann
2015-05-22 15:06 ` [Qemu-devel] [PULL 08/10] target-tricore: add FCALL instructions " Bastian Koppelmann
2015-05-22 15:06 ` [Qemu-devel] [PULL 09/10] target-tricore: add FRET " Bastian Koppelmann
2015-05-22 15:06 ` [Qemu-devel] [PULL 10/10] target-tricore: add RR_DIV and RR_DIV_U " Bastian Koppelmann
2015-05-22 16:19 ` [Qemu-devel] [PULL 00/10] tricore-patches Peter Maydell
-- strict thread matches above, loose matches on Subject: below --
2016-03-22 13:46 Bastian Koppelmann
2016-03-22 20:15 ` Peter Maydell
2016-03-23 8:17 ` Bastian Koppelmann
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