From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37033) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YvoWj-0007k6-Sl for qemu-devel@nongnu.org; Fri, 22 May 2015 11:06:27 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YvoWg-0007TH-If for qemu-devel@nongnu.org; Fri, 22 May 2015 11:06:21 -0400 Received: from mail.uni-paderborn.de ([131.234.142.9]:33084) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YvoWg-0007Sr-Bu for qemu-devel@nongnu.org; Fri, 22 May 2015 11:06:18 -0400 From: Bastian Koppelmann Date: Fri, 22 May 2015 17:05:58 +0200 Message-Id: <1432307168-10401-1-git-send-email-kbastian@mail.uni-paderborn.de> Subject: [Qemu-devel] [PULL 00/10] tricore-patches List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org The following changes since commit 8b6db32a4ec47d1171ccfa21d557096b99f4eef0: Merge remote-tracking branch 'remotes/stefanha/tags/block-pull-request' into staging (2015-05-22 13:25:40 +0100) are available in the git repository at: https://github.com/bkoppelmann/qemu-tricore-upstream.git tags/pull-tricore-20150522 for you to fetch changes up to 9371557115a734412974f8d4096cbe8a62ca2731: target-tricore: add RR_DIV and RR_DIV_U instructions of the v1.6 ISA (2015-05-22 17:02:34 +0200) ---------------------------------------------------------------- TriCore v1.6.1 ISA and missing v1.6 instructions ---------------------------------------------------------------- Bastian Koppelmann (10): target-tricore: Add ISA v1.3.1 cpu and fix tc1796 to using v1.3 target-tricore: introduce ISA v1.6.1 feature target-tricore: Add SRC_MOV_E instruction of the v1.6 ISA target-tricore: add CMPSWP instructions of the v1.6.1 ISA target-tricore: add SWAPMSK instructions of the v1.6.1 ISA target-tricore: add RR_CRC32 instruction of the v1.6.1 ISA target-tricore: add SYS_RESTORE instruction of the v1.6 ISA target-tricore: add FCALL instructions of the v1.6 ISA target-tricore: add FRET instructions of the v1.6 ISA target-tricore: add RR_DIV and RR_DIV_U instructions of the v1.6 ISA target-tricore/cpu.c | 18 ++++- target-tricore/cpu.h | 1 + target-tricore/helper.h | 4 + target-tricore/op_helper.c | 60 ++++++++++++++ target-tricore/translate.c | 166 ++++++++++++++++++++++++++++++++++++++- target-tricore/tricore-opcodes.h | 19 +++++ 6 files changed, 263 insertions(+), 5 deletions(-) -- 2.4.1