From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37036) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YvoWj-0007k9-TJ for qemu-devel@nongnu.org; Fri, 22 May 2015 11:06:29 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YvoWh-0007UA-D6 for qemu-devel@nongnu.org; Fri, 22 May 2015 11:06:21 -0400 Received: from mail.uni-paderborn.de ([131.234.142.9]:33089) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YvoWh-0007Ss-6N for qemu-devel@nongnu.org; Fri, 22 May 2015 11:06:19 -0400 From: Bastian Koppelmann Date: Fri, 22 May 2015 17:06:07 +0200 Message-Id: <1432307168-10401-10-git-send-email-kbastian@mail.uni-paderborn.de> In-Reply-To: <1432307168-10401-1-git-send-email-kbastian@mail.uni-paderborn.de> References: <1432307168-10401-1-git-send-email-kbastian@mail.uni-paderborn.de> Subject: [Qemu-devel] [PULL 09/10] target-tricore: add FRET instructions of the v1.6 ISA List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Signed-off-by: Bastian Koppelmann Reviewed-by: Richard Henderson --- target-tricore/translate.c | 19 +++++++++++++++++++ target-tricore/tricore-opcodes.h | 2 ++ 2 files changed, 21 insertions(+) diff --git a/target-tricore/translate.c b/target-tricore/translate.c index 76bab8e..d4e4226 100644 --- a/target-tricore/translate.c +++ b/target-tricore/translate.c @@ -3287,6 +3287,20 @@ static void gen_fcall_save_ctx(DisasContext *ctx) tcg_temp_free(temp); } +static void gen_fret(DisasContext *ctx) +{ + TCGv temp = tcg_temp_new(); + + tcg_gen_andi_tl(temp, cpu_gpr_a[11], ~0x1); + tcg_gen_qemu_ld_tl(cpu_gpr_a[11], cpu_gpr_a[10], ctx->mem_idx, MO_LESL); + tcg_gen_addi_tl(cpu_gpr_a[10], cpu_gpr_a[10], 4); + tcg_gen_mov_tl(cpu_PC, temp); + tcg_gen_exit_tb(0); + ctx->bstate = BS_BRANCH; + + tcg_temp_free(temp); +} + static void gen_compute_branch(DisasContext *ctx, uint32_t opc, int r1, int r2 , int32_t constant , int32_t offset) { @@ -3869,6 +3883,8 @@ static void decode_sr_system(CPUTriCoreState *env, DisasContext *ctx) case OPC2_16_SR_DEBUG: /* raise EXCP_DEBUG */ break; + case OPC2_16_SR_FRET: + gen_fret(ctx); } } @@ -7842,6 +7858,9 @@ static void decode_sys_interrupts(CPUTriCoreState *env, DisasContext *ctx) case OPC2_32_SYS_RET: gen_compute_branch(ctx, op2, 0, 0, 0, 0); break; + case OPC2_32_SYS_FRET: + gen_fret(ctx); + break; case OPC2_32_SYS_RFE: gen_helper_rfe(cpu_env); tcg_gen_exit_tb(0); diff --git a/target-tricore/tricore-opcodes.h b/target-tricore/tricore-opcodes.h index bb1939c..22c79f5 100644 --- a/target-tricore/tricore-opcodes.h +++ b/target-tricore/tricore-opcodes.h @@ -399,6 +399,7 @@ enum { OPC2_16_SR_RET = 0x09, OPC2_16_SR_RFE = 0x08, OPC2_16_SR_DEBUG = 0x0a, + OPC2_16_SR_FRET = 0x07, }; /* OPCM_16_SR_ACCU */ enum { @@ -1438,4 +1439,5 @@ enum { OPC2_32_SYS_TRAPSV = 0x15, OPC2_32_SYS_TRAPV = 0x14, OPC2_32_SYS_RESTORE = 0x0e, + OPC2_32_SYS_FRET = 0x03, }; -- 2.4.1