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From: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
To: qemu-devel@nongnu.org
Subject: [Qemu-devel] [PULL 07/10] target-tricore: add SYS_RESTORE instruction of the v1.6 ISA
Date: Fri, 22 May 2015 17:06:05 +0200	[thread overview]
Message-ID: <1432307168-10401-8-git-send-email-kbastian@mail.uni-paderborn.de> (raw)
In-Reply-To: <1432307168-10401-1-git-send-email-kbastian@mail.uni-paderborn.de>

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Reviewed-by: Richard Henderson <rth@twiddle.net>
---
 target-tricore/translate.c       | 10 ++++++++++
 target-tricore/tricore-opcodes.h |  1 +
 2 files changed, 11 insertions(+)

diff --git a/target-tricore/translate.c b/target-tricore/translate.c
index 52f474b..4aea0c6 100644
--- a/target-tricore/translate.c
+++ b/target-tricore/translate.c
@@ -7792,10 +7792,12 @@ static void decode_rrrw_extract_insert(CPUTriCoreState *env, DisasContext *ctx)
 static void decode_sys_interrupts(CPUTriCoreState *env, DisasContext *ctx)
 {
     uint32_t op2;
+    uint32_t r1;
     TCGLabel *l1;
     TCGv tmp;
 
     op2 = MASK_OP_SYS_OP2(ctx->opcode);
+    r1  = MASK_OP_SYS_S1D(ctx->opcode);
 
     switch (op2) {
     case OPC2_32_SYS_DEBUG:
@@ -7844,6 +7846,14 @@ static void decode_sys_interrupts(CPUTriCoreState *env, DisasContext *ctx)
     case OPC2_32_SYS_SVLCX:
         gen_helper_svlcx(cpu_env);
         break;
+    case OPC2_32_SYS_RESTORE:
+        if (tricore_feature(env, TRICORE_FEATURE_16)) {
+            if ((ctx->hflags & TRICORE_HFLAG_KUU) == TRICORE_HFLAG_SM ||
+                (ctx->hflags & TRICORE_HFLAG_KUU) == TRICORE_HFLAG_UM1) {
+                tcg_gen_deposit_tl(cpu_ICR, cpu_ICR, cpu_gpr_d[r1], 8, 1);
+            } /* else raise privilege trap */
+        } /* else raise illegal opcode trap */
+        break;
     case OPC2_32_SYS_TRAPSV:
         /* TODO: raise sticky overflow trap */
         break;
diff --git a/target-tricore/tricore-opcodes.h b/target-tricore/tricore-opcodes.h
index 440c7fe..d1506a9 100644
--- a/target-tricore/tricore-opcodes.h
+++ b/target-tricore/tricore-opcodes.h
@@ -1434,4 +1434,5 @@ enum {
     OPC2_32_SYS_SVLCX                            = 0x08,
     OPC2_32_SYS_TRAPSV                           = 0x15,
     OPC2_32_SYS_TRAPV                            = 0x14,
+    OPC2_32_SYS_RESTORE                          = 0x0e,
 };
-- 
2.4.1

  parent reply	other threads:[~2015-05-22 15:06 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-05-22 15:05 [Qemu-devel] [PULL 00/10] tricore-patches Bastian Koppelmann
2015-05-22 15:05 ` [Qemu-devel] [PULL 01/10] target-tricore: Add ISA v1.3.1 cpu and fix tc1796 to using v1.3 Bastian Koppelmann
2015-05-22 15:06 ` [Qemu-devel] [PULL 02/10] target-tricore: introduce ISA v1.6.1 feature Bastian Koppelmann
2015-05-22 15:06 ` [Qemu-devel] [PULL 03/10] target-tricore: Add SRC_MOV_E instruction of the v1.6 ISA Bastian Koppelmann
2015-05-22 15:06 ` [Qemu-devel] [PULL 04/10] target-tricore: add CMPSWP instructions of the v1.6.1 ISA Bastian Koppelmann
2015-05-22 15:06 ` [Qemu-devel] [PULL 05/10] target-tricore: add SWAPMSK " Bastian Koppelmann
2015-05-22 15:06 ` [Qemu-devel] [PULL 06/10] target-tricore: add RR_CRC32 instruction " Bastian Koppelmann
2015-05-22 15:06 ` Bastian Koppelmann [this message]
2015-05-22 15:06 ` [Qemu-devel] [PULL 08/10] target-tricore: add FCALL instructions of the v1.6 ISA Bastian Koppelmann
2015-05-22 15:06 ` [Qemu-devel] [PULL 09/10] target-tricore: add FRET " Bastian Koppelmann
2015-05-22 15:06 ` [Qemu-devel] [PULL 10/10] target-tricore: add RR_DIV and RR_DIV_U " Bastian Koppelmann
2015-05-22 16:19 ` [Qemu-devel] [PULL 00/10] tricore-patches Peter Maydell

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