From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39953) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YwHbM-0008WN-1s for qemu-devel@nongnu.org; Sat, 23 May 2015 18:09:04 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YwHbL-0005RQ-3U for qemu-devel@nongnu.org; Sat, 23 May 2015 18:09:03 -0400 Received: from mail-pa0-x22c.google.com ([2607:f8b0:400e:c03::22c]:34391) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YwHbK-0005RJ-Sz for qemu-devel@nongnu.org; Sat, 23 May 2015 18:09:03 -0400 Received: by pabru16 with SMTP id ru16so45064797pab.1 for ; Sat, 23 May 2015 15:09:02 -0700 (PDT) Sender: Richard Henderson From: Richard Henderson Date: Sat, 23 May 2015 15:06:54 -0700 Message-Id: <1432418814-7438-3-git-send-email-rth@twiddle.net> In-Reply-To: <1432418814-7438-1-git-send-email-rth@twiddle.net> References: <1432418814-7438-1-git-send-email-rth@twiddle.net> Subject: [Qemu-devel] [PATCH 2/2] linux-user: Add HWCAP for SH4 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: riku.voipio@iki.fi, dalias@libc.org, aurelien@aurel32.net Only exposing FPU and LLSC as the only features supported by the translator. Signed-off-by: Richard Henderson --- linux-user/elfload.c | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/linux-user/elfload.c b/linux-user/elfload.c index 0ba9706..b71e866 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -1075,6 +1075,35 @@ static inline void elf_core_copy_regs(target_elf_gregset_t *regs, #define USE_ELF_CORE_DUMP #define ELF_EXEC_PAGESIZE 4096 +enum { + SH_CPU_HAS_FPU = 0x0001, /* Hardware FPU support */ + SH_CPU_HAS_P2_FLUSH_BUG = 0x0002, /* Need to flush the cache in P2 area */ + SH_CPU_HAS_MMU_PAGE_ASSOC = 0x0004, /* SH3: TLB way selection bit support */ + SH_CPU_HAS_DSP = 0x0008, /* SH-DSP: DSP support */ + SH_CPU_HAS_PERF_COUNTER = 0x0010, /* Hardware performance counters */ + SH_CPU_HAS_PTEA = 0x0020, /* PTEA register */ + SH_CPU_HAS_LLSC = 0x0040, /* movli.l/movco.l */ + SH_CPU_HAS_L2_CACHE = 0x0080, /* Secondary cache / URAM */ + SH_CPU_HAS_OP32 = 0x0100, /* 32-bit instruction support */ + SH_CPU_HAS_PTEAEX = 0x0200, /* PTE ASID Extension support */ +}; + +#define ELF_HWCAP get_elf_hwcap() + +static uint32_t get_elf_hwcap(void) +{ + SuperHCPU *cpu = SUPERH_CPU(thread_cpu); + uint32_t hwcap = 0; + + hwcap |= SH_CPU_HAS_FPU; + + if (cpu->env.features & SH_FEATURE_SH4A) { + hwcap |= SH_CPU_HAS_LLSC; + } + + return hwcap; +} + #endif #ifdef TARGET_CRIS -- 2.1.0